MC12429FNR2 Freescale Semiconductor, MC12429FNR2 Datasheet

MC12429FNR2

Manufacturer Part Number

MC12429FNR2

Description

IC CLOCK SYNTHESIZER 28-PLCC

Manufacturer

Freescale Semiconductor

Type

Clock/Frequency Synthesizerr

Datasheet

1.MC12429FNR2.pdf (12 pages)

Specifications of MC12429FNR2

Pll

Yes

Input

Crystal

Output

PECL

Number Of Circuits

Ratio - Input:output

1:1

Differential - Input:output

No/Yes

Frequency - Max

400MHz

Divider/multiplier

Yes/No

Voltage - Supply

3.135 V ~ 5.25 V

Operating Temperature

0°C ~ 70°C

Mounting Type

Surface Mount

Package / Case

28-PLCC

Frequency-max

400MHz

Lead Free Status / RoHS Status

Contains lead / RoHS non-compliant

Other names

MC12429FNTR

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SEMICONDUCTOR TECHNICAL DATA

High Frequency Clock

Synthesizer

internal VCO will operate over a range of frequencies from 200 to

400MHz. The differential PECL output can be configured to be the VCO

frequency divided by 1, 2, 4, or 8. With the output configured to divide the

VCO frequency by 1, and with a 16.000MHz external quartz crystal used

to provide the reference frequency, the output frequency can be specified

in 1MHz steps. The PLL loop filter is fully integrated so that no external

components are required. The output frequency is configured using a

parallel or serial interface.

•

Functional Description

its frequency reference. The output of the reference oscillator is divided

by 16 before being sent to the phase detector. With a 16MHz crystal, this

provides a reference frequency of 1MHz. Although this data sheet

illustrates functionality only for a 16MHz crystal, any crystal in the

10–25MHz range can be used.

the serial or parallel interfaces. The output of this loop divider is also applied to the phase detector.

adjusting the VCO control voltage. Note that for some values of M (either too high or too low) the PLL will not achieve loop lock.

(N divider) is configured through either the serial or the parallel interfaces, and can provide one of four division ratios (1, 2, 4, or

8). This divider extends performance of the part while providing a 50% duty cycle.

in 50Ω to V CC – 2.0V. The positive reference for the output driver and the internal logic is separated from the power supply for the

phase–locked loop to minimize noise induced jitter.

inputs to configure the internal counters. Normally, on system reset, the P_LOAD input is held LOW until sometime after power

becomes valid. On the LOW–to–HIGH transition of P_LOAD, the parallel inputs are captured. The parallel interface has priority

over the serial interface. Internal pullup resistors are provided on the M[8:0] and N[1:0] inputs to reduce component count in the

application of the chip.

The serial input S_DATA must meet setup and hold timing as specified in the AC Characteristics section of this document. The

configuration latches will capture the value of the shift register on the HIGH–to–LOW edge of the S_LOAD input. See the

programming section for more information.

06/00

Motorola, Inc. 2000

25 to 400MHz Differential PECL Outputs

±25ps Peak–to–Peak Output Jitter

Fully Integrated Phase–Locked Loop

Minimal Frequency Over–Shoot

Synthesized Architecture

Serial 3–Wire Interface

Parallel Interface for Power–Up

Quartz Crystal Interface

28–Lead PLCC Package

Operates from 3.3V or 5.0V Power Supply

The MC12429 is a general purpose synthesized clock source. Its

The internal oscillator uses the external quartz crystal as the basis of

The VCO within the PLL operates over a range of 200 to 400MHz. Its output is scaled by a divider that is configured by either

The phase detector and loop filter attempt to force the VCO output frequency to be M times the reference frequency by

The output of the VCO is also passed through an output divider before being sent to the PECL output driver. This output divider

The output driver is driven differentially from the output divider, and is capable of driving a pair of transmission lines terminated

The configuration logic has two sections: serial and parallel. The parallel interface uses the values at the M[8:0] and N[1:0]

The serial interface centers on a fourteen bit shift register. The shift register shifts once per rising edge of the S_CLOCK input.

The TEST output reflects various internal node values, and is controlled by the T[2:0] bits in the serial data stream. See the

OTOROLA

REV 6

HIGH FREQUENCY PLL

CLOCK SYNTHESIZER

28–LEAD PLCC PACKAGE

C12429

CASE 776–02

FN SUFFIX

Order this document

by MC12429/D

Related parts for MC12429FNR2

MC12429FNR2 Summary of contents

Page 1

OTOROLA SEMICONDUCTOR TECHNICAL DATA High Frequency Clock Synthesizer The MC12429 is a general purpose synthesized clock source. Its internal VCO will operate over a range of frequencies from 200 to 400MHz. The differential PECL output can be configured to be ...

Page 2

MC12429 V CC FOUT FOUT GND S_CLOCK 26 S_DATA 27 S_LOAD 28 1 PLL_V XTAL1 XTAL2 OE P_LOAD PIN DESCRIPTIONS Pin Name Inputs XTAL1, XTAL2 These pins form an ...

Page 3

F REF DIV 16 4 XTAL1 16MHz OSC 5 XTAL2 S_LOAD 7 P_LOAD 27 S_DATA 26 S_CLOCK V CC1 21 +3.3 or 5.0V Programming the device amounts to properly configuring the internal dividers to produce the ...

Page 4

MC12429 Let 133.3333 ÷ 1.0416 256 The value for M falls within the constraints set for PLL stability, therefore N[1: and M[8:0} = 10000000. If the value for M fell ...

Page 5

FREF PLL 12429 MCNT SCLOCK M COUNTER SHIFT SDATA REG T0 14–BIT T1 T2 • T2=T1=1, T0=0: Test Mode (PLL bypass) • SCLOCK is selected, MCNT is on TEST output, SCLOCK DIVIDE FOUT pin PLOADB acts ...

Page 6

MC12429 AC CHARACTERISTICS ( 0° to 70° 3.3V to 5.0V ±5%) Symbol Characteristic F MAXI Maximum Input Frequency F MAXO Maximum Output Frequency t LOCK Maximum PLL Lock Time t jitter Period Deviation (Peak–to–Peak) t ...

Page 7

Power Supply Filtering The MC12429 is a mixed analog/digital product and as such it exhibits some sensitivities that would not necessarily be seen on a fully digital product. Analog circuitry is naturally susceptible to random noise, especially if this noise ...

Page 8

MC12429 be applications in which overall performance is being degraded due to system power supply noise. The power supply filter and bypass schemes discussed in this section should be adequate to eliminate power supply noise related problems in most designs. ...

Page 9

0.010 (0.250 L– NOTES: 1. DATUMS –L–, –M–, AND –N– DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. ...

Page 10

MC12429 Revision History Revision Min Rev 6 06/00 MOTOROLA Date PECL V OH and V OL values in DC output characteristics table were changed from 100E to 10E (10H) style. Output levels represent a greater differential output swing and reflect ...

Page 11

TIMING SOLUTIONS BR1333 — Rev 6 NOTES 11 MC12429 MOTOROLA ...

Page 12

MC12429 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out ...

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