SI4133GX2-BM Silicon Laboratories Inc, SI4133GX2-BM Datasheet

SYNTH DUAL GSM RF(RF1/RF2/IF)

SI4133GX2-BM

Manufacturer Part Number
SI4133GX2-BM
Description
SYNTH DUAL GSM RF(RF1/RF2/IF)
Manufacturer
Silicon Laboratories Inc
Type
Frequency Synthesizerr
Datasheets

Specifications of SI4133GX2-BM

Pll
Yes
Input
Clock
Output
Clock
Number Of Circuits
1
Ratio - Input:output
1:2
Differential - Input:output
No/No
Frequency - Max
1.8GHz
Divider/multiplier
Yes/No
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-20°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
28-QFN
Frequency-max
1.8GHz
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
D
F
Features
Applications
Description
The Si4133G-X2 is a monolithic integrated circuit that performs both IF and
dual-band RF synthesis for GSM and GPRS wireless communications
applications. The Si4133G-X2 includes three VCOs, loop filters, reference
and VCO dividers, and phase detectors. Divider and powerdown settings are
programmable through a three-wire serial interface.
Functional Block Diagram
Rev. 1.2 5/03
AUXOUT
O R
U A L
SDATA
PWDN
SCLK
Dual-band RF synthesizers
IF synthesizer
Integrated VCOs, loop filters,
varactors, and resonators
Minimal number of external
components required
GSM 850, E-GSM 900, DCS 1800, and PCS 1900 cellular
telephones
GPRS data terminals
HSCSD data terminals
SEN
XIN
RF1: 900 MHz to 1.8 GHz
RF2: 750 MHz to 1.5 GHz
1070.4, 1080, and 1089.6 MHz
G S M
- B
Powerdown
Reference
Amplifier
Interface
Register
A N D
Control
Serial
22-bit
Data
Test
Mux
A N D
R F S
÷
65
G P R S W
Y N T H E S I Z E R
Detector
Detector
Detector
Phase
Phase
Phase
Copyright © 2003 by Silicon Laboratories
I R E L E S S
÷
÷
÷
Optimized for use with Hitachi
Bright2+ transceiver
Settling time < 150 µs
Low phase noise
Programmable powerdown
modes
1 µA standby current
18 mA typical supply current
2.7 to 3.6 V operation
Packages: 24-pin TSSOP and
28-pin MLP
N
N
N
RF1
RF2
IF
W
I T H
C
O M M U N I C A T I O N S
I
N T E G R A T E D
RFLA
RFLB
RFOUT
RFLC
RFLD
IFOUT
IFLA
IFLB
S i 4 1 3 3 G - X 2
Patents pending
GNDR
GNDR
GNDR
RFLD
RFLC
RFLB
RFLA
V C O
RFOUT
VDDR
SDATA
GNDR
GNDR
GNDR
GNDR
RFLD
RFLC
RFLB
RFLA
SCLK
1
2
3
4
5
6
7
Ordering Information
28 27 26 25 24 23 22
Pin Assignments
8
Si4133G-XM2
S
Si4133G-XT2
See page 24.
10
11
12
1
2
3
4
5
6
7
8
9
9
10 11 12 13 14
GND
Pad
Si4133GX2-DS12
24
23
22
21
20
19
18
17
16
15
14
13
SEN
VDDI
IFOUT
GNDI
IFLB
IFLA
GNDD
VDDD
GNDD
XIN
PWDN
AUXOUT
21
20
19
18
17
16
15
GNDI
IFLB
IFLA
GNDD
VDDD
GNDD
XIN

Related parts for SI4133GX2-BM

SI4133GX2-BM Summary of contents

Page 1

... RFLA VDDD 9 16 GNDR GNDD 10 15 GNDR XIN 11 14 RFOUT PWDN 12 13 VDDR AUXOUT Si4133G-XM2 GNDR GNDI 2 20 RFLD IFLB 3 19 RFLC IFLA GND 4 18 GNDR GNDD Pad 5 17 RFLB VDDD 6 16 RFLA GNDD 7 15 GNDR XIN Patents pending Si4133GX2-DS12 ...

Page 2

Si4133G-X2 2 Rev. 1.2 ...

Page 3

Section Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . ...

Page 4

Si4133G-X2 Electrical Specifications Table 1. Recommended Operating Conditions Parameter Ambient Temperature Supply Voltage Supply Voltages Difference Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at 3.0 V and an operating ...

Page 5

Table 3. DC Characteristics (V = 2 – ° Parameter 1 Total Supply Current 1 RF1 Mode Supply Current 1 RF2 Mode Supply Current 1 IF Mode Supply Current Standby Current ...

Page 6

Si4133G-X2 Table 4. Serial Interface Timing (V = 2 – ° Parameter SCLK Cycle Time SCLK Rise Time SCLK Fall Time SCLK High Time SCLK Low Time 2 SDATA Setup ...

Page 7

SCLK SDATA D17 t en1 SEN Figure 2. Serial Interface Timing Diagram First bit c loc ked Figure 3. Serial Word Format t hold D16 ...

Page 8

Si4133G-X2 Table 5. RF and IF Synthesizer Characteristics (V = 2 – ° Parameter XIN Input Frequency Reference Amplifier Sensitivity Internal Phase Detector Frequency RF1 VCO Center Frequency Range RF2 ...

Page 9

Table 5. RF and IF Synthesizer Characteristics (Continued 2 – ° Parameter RF1 Reference Spurs F2 Reference Spurs R Powerup Request to Synthesizer Ready 2 Time, RF1, RF2, ...

Page 10

Si4133G-X2 TRACE A: Ch1 FM Gate Time A Offset 800 Hz Real 160 Hz /div -800 Hz Start Figure 6. Typical Transient Response RF1 at 1.6 GHz with 200 kHz Phase Detector Update Frequency 10 133.59375 us Stop: ...

Page 11

Figure 7. Typical RF1 Phase Noise at 1.6 GHz with 200 kHz Phase Detector Update Frequency Figure 8. Typical RF1 Spurious Response at 1.6 GHz with 200 kHz Phase Detector Update Frequency Rev. 1.2 Si4133G-X2 11 ...

Page 12

Si4133G-X2 Figure 9. Typical RF2 Phase Noise at 1.2 GHz with 200 kHz Figure 10. Typical RF2 Spurious Response at 1.2 GHz with 200 kHz 12 Phase Detector Update Frequency Phase Detector Update Frequency Rev. 1.2 ...

Page 13

Figure 11. Typical IF Phase Noise at 1080 MHz with 200 kHz Phase Detector Update Frequency Figure 12. IF Spurious Response at 1080 MHz with 200 kHz Phase Detector Update Frequency Rev. 1.2 Si4133G-X2 13 ...

Page 14

Si4133G-X2 Typical Application Circuits From System Controller Printed Trace Inductors 560 RFOUT 0.022 µF V From System Controller Printed Trace 4 Inductors PWDN 14 Si4133G-XT2 SEN SCLK 2 ...

Page 15

Functional Description The Si4133G- monolithic integrated circuit that performs IF and dual-band RF synthesis for many wireless applications such as GSM 850, E-GSM 900, DCS 1800, and PCS 1900. Its fast transient response also makes the Si4133G-X2 especially ...

Page 16

Si4133G-X2 Tables 6 and 7 summarize these characteristics for each VCO. Table 6. Si4133G-XT2 VCO Characteristics VCO f Range C L CEN NOM PKG (MHz) (pF) (nH) Min Max RF1 947 1720 4.3 2.0 RF2 789 1429 4.8 2.3 IF ...

Page 17

The LDETB signal is low after self-tuning has completed but rises when either the PLL nears the limit of its compensation range (LDETB is also high when either PLL is executing the self-tuning algorithm). The output frequency ...

Page 18

Si4133G-X2 560 IFOUT Figure 17. IFOUT 50 Ω Matching Network Reference Frequency Amplifier The Si4133G-X2 provides a reference frequency amplifier. If the driving signal has CMOS levels it can be connected directly to the XIN pin. Otherwise, ...

Page 19

Control Registers Register Name Bit Bit Main 0 0 Configuration 1 Reserved 2 Powerdown RF1 N- Divider 4 RF2 N- 0 Divider 5 IF N-Divider Reserved . . . 15 Reserved ...

Page 20

Si4133G-X2 Register 0. Main Configuration Address Field = A[3:0] = 0000 Bit D17 D16 D15 D14 D13 D12 D11 D10 D9 Name AUXSEL Bit Name 17:14 Reserved 13:12 AUXSEL[1:0] 11:4 Reserved 3 AUTOPDB 2 Reserved 1 ...

Page 21

Register 3. RF1 N-Divider Address Field (A[3:0]) = 0011 Bit D17 D16 D15 D14 D13 D12 D11 D10 Name Bit Name 17:0 N [17:0] N-Divider for RF1 Synthesizer. RF1 Register 4. RF2 N-Divider Address Field = A[3:0] = 0100 Bit ...

Page 22

Si4133G-X2 Pin Descriptions: Si4133G-XT2 Pin Number Name Description 1 SCLK Serial clock input 2 SDATA Serial data input 3 GNDR Common ground for RF analog circuitry 4 RFLD Pins for inductor connection to RF2 VCO 5 RFLC Pins for inductor ...

Page 23

Pin Descriptions: Si4133G-XM2 Pin Number Name Description 1 GNDR Common ground for RF analog circuitry 2 RFLD Pins for inductor connection to RF2 VCO 3 RFLC Pins for inductor connection to RF2 VCO 4 GNDR Common ground for RF analog ...

Page 24

Si4133G-X2 Ordering Guide Ordering Part Number Si4133G-XM2 Si4133G-XT2 24 Description Package RF1/RF2/IF OUT 28-Pin MLP RF1/RF2/IF OUT 24-Pin TSSOP Rev. 1.2 Temperature o – – ...

Page 25

Package Outline: Si4133G-XT2 Figure 18 illustrates the package details for the Si4133G-XT2. Table 10 lists the values for the dimensions shown in the illustration. D γ Figure 18. 24-Pin Thin Shrink Small Outline Package (TSSOP) Table 10. Package Diagram Dimensions ...

Page 26

Si4133G-X2 Package Outline: Si4133G-XM2 Figure 19 illustrates the package details for the Si4113G-XM2. Table 11 lists the values for the dimensions shown in the illustration D TOP VIEW Figure 19. 28-Pin Micro ...

Page 27

Document Change List Revision 1.1 to Revision 1.2 TSSOP outline updated. Si4133G-X2 Rev. 1.2 27 ...

Page 28

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