SI5316-B-GM Silicon Laboratories Inc, SI5316-B-GM Datasheet - Page 10

• Manufacturer Part Number: SI5316-B-GM
• Description: IC PREC JITTER ATTENUATOR 36QFN
• Manufacturer: Silicon Laboratories Inc
• Type: Clock Jitter Attenuatorr

Specifications of SI5316-B-GM

• Number Of Circuits: 1
• Package / Case: 36-QFN
• Pll: Yes with Bypass
• Input: Clock
• Output: CML, CMOS, LVDS, LVPECL
• Ratio - Input:output: 2:1
• Differential - Input:output: Yes/Yes
• Frequency - Max: 710MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 1.62 V ~ 3.63 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Frequency-max: 710MHz
• Maximum Input Frequency: 710 MHz
• Minimum Input Frequency: 19.38 MHz
• Output Frequency Range: 19.38 MHz to 710 MHz
• Supply Voltage (max): 3.63 V
• Supply Voltage (min): 1.71 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 1.8 V, 2.5 V, 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

GND PAD
*Note: Denotes 3-Level input pin with states designated as L (ground), M (VDD/2), and H (VDD).
Si5316
10
Pin #
33
30
34
35
Pin Name
CKOUT+
SFOUT0
SFOUT1
CKOUT–
GND
GND
I/O
O
I
Table 3. Si5316 Pin Descriptions (Continued)
Signal Level
3-Level
Supply
Multi
Signal Format Select.
Three level inputs that select the output signal format (common
mode voltage and differential swing) for CKOUT. Valid settings
include LVPECL, LVDS, and CML. Also includes selections for
CMOS mode, tristate mode, and tristate/sleep mode.
These pins have both weak pull-ups and weak pull-downs and
default to M.
Some designs may require an external resistor voltage divider when
driven by an active device that will tri-state.
Clock Output.
Differential output clock with a frequency selected from a table of val-
ues. Output signal format is selected by SFOUT pins. Output is differ-
ential for LVPECL, LVDS, and CML compatible modes. For CMOS
format, both output pins drive identical single-ended clock outputs.
Ground Pad.
The ground pad must provide a low thermal and electrical impedance
to a ground plane.
Rev. 0.4
SFOUT[1:0]
MM
HM
MH
HH
ML
LM
HL
LH
LL
Description
LVDS
Reserved
CML
LVPECL
Reserved
LVDS—low swing
CMOS
Disabled
Reserved
Signal Format