M41T81SM6F STMicroelectronics, M41T81SM6F Datasheet
M41T81SM6F
Specifications of M41T81SM6F
Available stocks
Related parts for M41T81SM6F
M41T81SM6F Summary of contents
Page 1
Features ■ Counters for tenths/hundredths of seconds, seconds, minutes, hours, day, date, month, year, and century ■ 32 KHz crystal oscillator with integrated load capacitance (12.5 pf) which provides exceptional oscillator stability and high crystal series resistance operation) ■ Oscillator ...
Page 2
Contents Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 3
M41T81S 7 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 4
List of tables List of tables Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 5
M41T81S List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 6
Description 1 Description The M41T81S is a low power serial RTC with a built-in 32.768 kHz oscillator (external crystal controlled). Eight bytes of the SRAM are used for the clock/calendar function and are configured in binary coded decimal (BCD) format. ...
Page 7
M41T81S Table 1. Signal names (1) XI (1) XO IRQ/OUT/FT/SQW SDA SCL V BAT ( For SO8 package only and NF pins should be tied to V Figure 2. 8-pin ...
Page 8
Description Figure 4. Block diagram CRYSTAL SDA SCL BAT PFD 1. Open drain output 2. Square wave function has the highest priority on IRQ/FT/OUT/SQW output. 8/32 REAL TIME CLOCK CALENDAR OSCILLATOR FAIL CIRCUIT 32KHz ...
Page 9
M41T81S 2 Operation The M41T81S clock operates as a slave device on the serial bus. Access is obtained by implementing a start condition followed by the correct slave address (D0h). The 20 bytes contained in the device can then be ...
Page 10
Operation Accordingly, the following bus conditions have been defined: Bus not busy Both data and clock lines remain high. Start data transfer A change in the state of the data line, from high to low, while the clock is high, ...
Page 11
M41T81S Figure 5. Serial bus data transfer sequence CLOCK DATA START CONDITION Figure 6. Acknowledgement sequence SCL FROM MASTER DATA OUTPUT BY TRANSMITTER DATA OUTPUT BY RECEIVER READ mode In this mode the master reads the M41T81S slave after setting ...
Page 12
Operation An alternate READ mode may also be implemented whereby the master reads the M41T81S slave without first writing to the (volatile) address pointer. The first address that is read is the last one stored in the pointer (see Figure ...
Page 13
M41T81S WRITE mode In this mode the master transmitter transmits to the M41T81S slave receiver. Bus protocol is shown in Figure 10 on page (R/W=0) is placed on the bus and indicates to the addressed device that word address “An” ...
Page 14
Clock operation 3 Clock operation The 20-byte register map (see the clock and to read the date and time from the clock binary coded decimal format. Tenths/hundredths of seconds, seconds, minutes, and hours are contained within the first ...
Page 15
M41T81S Table 2. Clock register map Addr D7 D6 00h 0.1 seconds 01h ST 02h 0 03h CEB CB 04h 0 05h 0 06h 0 07h 08h OUT FT 09h OFIE BMB4 BMB3 BMB2 BMB1 BMB0 0Ah AFE SQW 0Bh ...
Page 16
Clock operation Calibrating the clock The M41T81S is driven by a quartz controlled oscillator with a nominal frequency of 32,768 Hz. The devices are tested not exceed ±35 ppm (parts per million) oscillator frequency error at 25 Figure 11 on ...
Page 17
M41T81S The IRQ/FT/OUT/SQW pin is an open drain output which requires a pull-up resistor to V for proper operation. A 500-10k resistor is recommended in order to control the rise time. The FT bit is cleared on power-down. Figure 11. ...
Page 18
Clock operation When the clock information matches the alarm clock settings based on the match criteria defined by RPT5-RPT1, the AF (alarm flag) is set. If AFE (alarm flag enable) is also set (and SQWE is '0.'), the alarm condition ...
Page 19
M41T81S Table 3. Alarm repeat modes RPT5 RPT4 Watchdog timer The watchdog timer can be used to detect an out-of-control microprocessor. The user programs the watchdog timer by ...
Page 20
Clock operation Square wave output The M41T81S offers the user a programmable square wave function which is output on the SQW pin. RS3-RS0 bits located in 13h establish the square wave output frequency. These frequencies are listed in completed, the ...
Page 21
M41T81S Battery low warning The M41T81S automatically performs battery voltage monitoring upon power-up and at factory-programmed time intervals of approximately 24 hours. The battery low (BL) bit, bit D4 of flags register 0Fh, will be asserted if the battery voltage ...
Page 22
Clock operation Output driver pin When the FT bit, AFE bit, SQWE bit, and watchdog register are not set, the IRQ/FT/OUT/SQW pin becomes an output driver that reflects the contents the calibration register. In other words, when ...
Page 23
M41T81S 4 Maximum ratings Stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions ...
Page 24
DC and AC parameters 5 DC and AC parameters This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC Characteristic tables are derived ...
Page 25
... V Backup supply voltage BAT I Battery supply current BAT 1. Valid for ambient operating temperature For IRQ/FT/OUT/SQW pin (open drain) 3. STMicroelectronics recommends the RAYOVAC BR1225 or BR1632 (or equivalent) as the battery supply. 4. For rechargeable back-up, V Table 10. Crystal electrical characteristics Sym f Resonant frequency O R Series resistance ...
Page 26
DC and AC parameters Table 11. Power down/up AC characteristics Symbol t SCL and SDA rec 1. V fall time should not exceed 5 mV/µ Valid for ambient operating temperature: T Table 12. Power ...
Page 27
M41T81S Table 13. AC characteristics Sym f SCL clock frequency SCL t Clock low period LOW t Clock high period HIGH t SDA and SCL rise time R t SDA and SCL fall time F START condition hold time t ...
Page 28
Package mechanical data 6 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available ...
Page 29
M41T81S Figure 19. SOX18 – 18-lead plastic small outline, 300 mils, embedded crystal, outline Note: Drawing is not to scale. Table 15. SOX18 – 18-lead plastic small outline, 300 mils, embedded crystal, package mechanical data Symbol ...
Page 30
Part numbering 7 Part numbering Table 16. Ordering information Example: Device type M41T Supply voltage and write protect voltage 81S = V = 2 Package M = SO8 ( SOX18 Temperature range 6 = ...
Page 31
M41T81S 8 Revision history Date Revision 22-Jan-2004 0.1 First draft Update BL information, characteristics, ratings, and Lead (Pb)-free information 06-Feb-2004 0.2 (Table 20-Feb-2004 0.3 Update characteristics Product promoted; reformatted; update characteristics, including Lead-free 14-Apr-2004 1 package information Table 05-May-2004 1.1 ...
Page 32
... Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...