ISL12024IBZ-T Intersil, ISL12024IBZ-T Datasheet
ISL12024IBZ-T
Specifications of ISL12024IBZ-T
Related parts for ISL12024IBZ-T
ISL12024IBZ-T Summary of contents
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... NUMBER PART V RANGE DD (Note) MARKING RANGE (°C) ISL12024IBZ* 12024 IBZ 2.7V to - SOIC 5.5V ISL12024IVZ* 2024 IVZ 2.7V to - TSSOP M8.173 5.5V *Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ ...
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Block Diagram X1 32.768kHz X2 IRQ/F OUT SELECT CONTROL SERIAL SCL DECODE INTERFACE LOGIC DECODER SDA 8 Pin Descriptions PIN NUMBER SOIC TSSOP SYMBOL The X1 pin is the input of an inverting amplifier and is intended ...
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... Output Low Voltage OL I Output Leakage Current LO 3 ISL12024 Thermal Information OUT Pins Thermal Resistance (Typical, Note SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . 8 Ld TSSOP Package . . . . . . . . . . . . . . . . . . . . . . . Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Pb-Free Reflow Profile .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp = +2.7V to +5.5V 3.3V. CONDITIONS CONDITIONS 2.7V ...
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EEPROM Specifications PARAMETER EEPROM Endurance EEPROM Retention 2 Serial Interface (I C) Specifications DC Electrical Specifications SYMBOL PARAMETER V SDA, and SCL Input Buffer LOW IL Voltage V SDA, and SCL Input Buffer HIGH IH Voltage Hysteresis SDA and SCL ...
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AC Electrical Specifications (Continued) SYMBOL PARAMETER Cpin SDA and SCL Pin Capacitance t Non-Volatile Write Cycle Time WC t SDA and SCL Rise Time R t SDA and SCL Fall Time F Cb Capacitive Loading of SDA or SCL R ...
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Typical Performance Curves 4.0 BSW = 3.5 SCL, SDA PULL-UPS = 0V 3.0 2.5 2.0 1.5 SCL, SDA PULL-UPS = V 1.0 0.5 BSW = 0.0 1.8 2.3 2.8 3.3 3.8 V (V) BAT ...
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Description The ISL12024 device is a Real-Time Clock with clock/calendar, 64-bit unique ID, two polled alarms with integrated 512x8 EEPROM, oscillator compensation and battery backup switch. The oscillator uses an external, low-cost 32.768kHz crystal. All compensation and trim components are ...
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... For example, a >20ppm frequency deviation translates into an accuracy of >1 minute per month. These parameters are available from the crystal manufacturer. Intersil’s RTC family provides on-chip crystal compensation networks to adjust load-capacitance to tune oscillator frequency from -34ppm to +80ppm when using a 12.5pF load crystal. For more detailed information see the “ ...
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Hour Time If the MIL bit of the HR register is 1, the RTC uses a 24-hour format. If the MIL bit is 0, the RTC uses a 12-hour format and H21-bit functions as an AM/PM indicator with a ...
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REG ADDR. TYPE NAME 7 003F Status SR BAT 0037 RTC Y2K 0 (SRAM) 0036 DW 0 0035 YR Y23 0034 MO 0 0033 DT 0 0032 HR MIL 0031 MN 0 0030 SC 0 0027 ID7 ID77 0026 ID6 ...
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Alarm Registers (Non-Volatile) Alarm0 and Alarm1 The alarm register bytes are set up identical to the RTC register bytes, except that the MSB of each byte functions as an enable bit (enable = “1”). These enable bits specify which alarm ...
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The effective on-chip series load capacitance, C ranges from 4.5pF to 20.25pF with a mid-scale value of 12.5pF (default changed via two digitally LOAD controlled capacitors, C and C , connected from the and X2 ...
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... Many types of batteries can be used with Intersil RTC products. For example, 3.0V or 3.6V Lithium batteries are appropriate, and battery sizes are available that can power an Intersil RTC device for years. Another option is to use a Super Cap for applications where V for month. See the “Application Section” on page 20 for more information ...
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To trigger the delay, the VDD must drop below the battery trip point, yet stay above approximately 1.0V (limit of active circuit operation). After that, the power-up ramp must be slower than 0.25V/ms to trigger ...
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Start Condition All commands are preceded by the start condition, which is a HIGH to LOW transition of SDA when SCL is HIGH. The device continuously monitors the SDA and SCL lines for the start condition and will not respond ...
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Device Addressing Following a start condition, the master must output a Slave Address Byte. The first four bits of the Slave Address Byte specify access to either the EEPROM array or to the CCR. Slave bits ‘1010’ access the EEPROM ...
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Write Operations Byte Write For a write operation, the device requires the Slave Address Byte and the Word Address Bytes. This gives the master access to any one of the words in the array or CCR. (Note: Prior to writing ...
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S T SIGNALS FROM A THE MASTER R SLAVE T ADDRESS SDA BUS 1 SIGNALS FROM THE SLAVE Acknowledge Polling Disabling of the inputs during non-volatile write cycles can be used to take advantage of the 12ms (typ) write cycle ...
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It should be noted that the ninth clock cycle of the read operation is not a “don’t care.” To terminate a read operation, the master must either issue a stop condition during the ninth cycle or hold SDA HIGH during ...
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... In addition to the analog compensation afforded by the adjustable load capacitance, a digital compensation feature is available for the Intersil RTC family. There are 3-bits known as the Digital Trimming Register or DTR, and they operate by adding or skipping pulses in the clock signal. The range provided is ± ...
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... Backup Battery Operation Many types of batteries can be used with the Intersil RTC products. 3.0V or 3.6V Lithium batteries are appropriate, and sizes are available that can power a Intersil RTC device for years. Another option is to use a supercapacitor for applications where V short periods of time. Depending on the value of the Super Cap used, backup time can last from a few days to two weeks (with > ...
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V V 2.7V TO 5.5V DD BAT V SS FIGURE 24. SUPER CAPACITOR CHARGING CIRCUIT Alarm Operation Examples Below are examples of both Single Event and periodic Interrupt Mode alarms. EXAMPLE 1 Alarm0 set with single interrupt (IM = “0”) ...
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V , then the device will enter Battery Backup Mode and BAT 2 the I C interface will be disabled, minimizing V drain. • Mode D - This mode combines Legacy Mode battery 2 switchover with operation ...
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Small Outline Plastic Packages (SOIC) N INDEX 0.25(0.010) H AREA E - SEATING PLANE - -C- α 0.10(0.004) 0.25(0.010 NOTES: 1. Symbols are defined in the ...
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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...