ISL1209IU10Z Intersil, ISL1209IU10Z Datasheet
ISL1209IU10Z
Specifications of ISL1209IU10Z
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ISL1209IU10Z Summary of contents
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... MARKING (V) (°C) ISL1209IU10 AGT 2.7 to 5.5 - MSOP M10.118 ISL1209IU10Z ANV 2.7 to 5.5 - MSOP (Note) *Add “-TK” suffix for tape and reel. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations ...
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Block Diagram SDA SDA BUFFER SCL SCL BUFFER X1 CRYSTAL OSCILLATOR TRIP V BAT EVIN GND Pin Descriptions PIN NUMBER SYMBOL 1 X1 X1. The X1 pin is the input of an inverting amplifier and is ...
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Absolute Maximum Ratings Voltage SCL, SDA, and IRQ pins DD BAT (respect to ground ...
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I C Interface Specifications Test Conditions:V SYMBOL PARAMETER V SDA and SCL input buffer LOW IL voltage V SDA and SCL input buffer HIGH IH voltage Hysteresis SDA and SCL input buffer hysteresis V SDA output buffer LOW voltage, ...
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SDA vs SCL Timing SCL t SU:STA t HD:STA SDA (INPUT TIMING) SDA (OUTPUT TIMING) Symbol Table WAVEFORM INPUTS Must be steady May change from LOW to HIGH May change from HIGH to LOW Don’t Care: Changes Allowed N/A 5 ...
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VDD Typical Performance Curves 1E-6 900E-9 800E-9 700E-9 600E-9 500E-9 400E-9 300E-9 200E-9 100E-9 000E+0 1.5 2.0 2.5 3.0 3.5 4.0 V (V) BAT FIGURE BAT 2.4E-06 2.2E- 2.0E-06 1.8E-06 1.6E-06 V ...
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EQUIVALENT AC OUTPUT LOAD CIRCUIT FOR V 5.0V 1533Ω SDA AND IRQ/FOUT 100pF FIGURE 7. STANDARD OUTPUT LOAD FOR TESTING THE DEVICE WITH V = 5.0V DD General Description The ISL1209 device is a low power Real Time Clock with ...
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... Power Control Operation The power control circuit accepts Many types of batteries can be used with Intersil RTC products. For example, 3.0V or 3.6V Lithium batteries are appropriate, and battery sizes are available that can power the ISL1209 for years. Another option is to use a ...
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Power Mode, is available to allow direct switching from without requiring V to drop below V BAT DD the additional monitoring needed, that circuitry is shut down and less power is used ...
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Users have the option to connect EVIN (see EVINEB bit internal pull up current source that operates at 1 (always on mode). User selectable event sampling modes are also available which will effectively reduce power consumption with 1/4-Hz, ...
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I C Serial Interface 2 The ISL1209 has serial bus interface that provides access to the control and status registers and the user 2 SRAM. The I C serial interface is compatible with other 2 industry ...
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REG ADDR. SECTION NAME 7 00h SC 0 01h MN 0 02h HR MIL 03h RTC DT 0 04h MO 0 05h YR YR23 06h DW 0 07h SR ARST XTOSCB Reserved 08h INT IM Control 09h and EV EVIENB ...
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Real Time Clock Registers Addresses [00h to 06h] RTC REGISTERS (SC, MN, HR, DT, MO, YR, DW) These registers depict BCD representations of the time. As such, SC (Seconds) and MN (Minutes) range from 0 to 59, HR (Hour) can ...
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AUTO RESET ENABLE BIT (ARST) This bit enables/disables the automatic reset of the BAT and ALM status bits only. When ARST bit is set to “1”, these status bits are reset to “0” after a valid read of the respective ...
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EVENT INPUT TIME BASE HYSTERESIS SELECTION BITS (EHYS<1:0>) These two bits select the time base hysteresis of the EVIN pin to filter bouncing or noise of external event detection circuits. The time filter can be set between 0 to 31.25 ...
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TABLE 12. BMATR1 BMATR0 0 0 0pF 0 1 -0.5pF (≈ +2ppm +0.5pF (≈ -2ppm +1pF (≈ -4ppm) DIGITAL TRIMMING REGISTER (DTR <2:0>) The digital trimming bits DTR0, DTR1, and DTR2 adjust the average number of ...
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After these registers are set, an alarm will be generated when the RTC advances to exactly 11:30am on January 1 (after seconds changes from 59 to 00) by setting the ALM bit in the status register to “1” and also ...
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SCL SDA START FIGURE 12. VALID DATA CHANGES, START, AND STOP CONDITIONS SCL FROM MASTER SDA OUTPUT FROM TRANSMITTER HIGH IMPEDANCE SDA OUTPUT FROM RECEIVER START FIGURE 13. ACKNOWLEDGE RESPONSE FROM RECEIVER SIGNALS FROM S THE MASTER T IDENTIFICATION A ...
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Device Addressing Following a start condition, the master must output a Slave Address Byte. The 7 MSBs are the device identifier. These bits are “1101111”. Slave bits “1101” access the register. Slave bits “111” specify the device select bits. The ...
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Application Section Event Detection The event detection feature of the ISL1209 is intended to be used for recording the time of single events that involve the opening of an enclosure, door, etc. The normal method of detection is with normally ...
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V input to allow event detection in battery BAT backup. Note that any input signal conditioning circuitry that is added in regular operation or battery backup should have minimum supply current drain, or have the capability ...
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If full industrial temperature compensation is desired in an ISL1209 circuit, then both the DTR and ATR registers will need to be utilized (total correction range = -94 to +140ppm). A system to implement temperature compensation would consist of the ...
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Below are some examples with equations to assist with calculating backup times and required capacitance for the ISL1209 device. The backup supply current plays a major part in these equations, and a typical value was chosen for example purposes. For ...
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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...