DS1687-3 Maxim Integrated Products, DS1687-3 Datasheet
DS1687-3
Specifications of DS1687-3
Available stocks
Related parts for DS1687-3
DS1687-3 Summary of contents
Page 1
... RAM Clear Input Century Register Date Alarm Register Compatible with Existing BIOS for Original DS1287 Functions Available as Chip (DS1685) or Stand-Alone Encapsulated DIP (EDIP) with Embedded Battery and Crystal (DS1687) Timekeeping Algorithm Includes Leap-Year Compensation Valid Through 2099 Underwriters Laboratory (UL) Recognized PWR ...
Page 2
... SO (0.300”)/Tape & Reel 3 24 EDIP (0.740” EDIP (0.740” EDIP (0.740” EDIP (0.740” TOP MARK* DS1685-3 DS1685-5 DS1685-5 DS1685E-3 DS1685E DS1685E-3 DS1685E DS1685E-3 DS1685E DS1685E-3 DS1685E DS1685Q-3 DS1685Q-5 DS1685Q-3 DS1685Q-5 DS1685Q-3 DS1685Q-5 DS1685S-3 DS1685S-5 DS1685S-3 DS1685S-5 DS1687-3 DS1687-5 DS1687-3 DS1687-5 ...
Page 3
... NV SRAM, and 32.768kHz output for sustaining power management activities. The DS1685/DS1687 power-control circuitry allows the system to be powered external stimulus such as a keyboard time and date (wake-up) alarm. The PWR output pin can be triggered by one or either of these events, and can be used to turn on an external power supply ...
Page 4
... WR signal defines the time period during which data is written to the addressed register. Read Input, Active Low. RD identifies the time period when the DS1685/DS1687 drives the bus with RTC read data. The RD signal enable signal for the output buffers of the clock DS1685/DS1687 3V/5V Real-Time Clocks ...
Page 5
... NAME Kickstart Input, Active Low. When V DS1685/DS1687, the system can be powered on in response to an active- low transition on the KS pin, as might be generated from a key closure. V must be present and the auxiliary-battery enable bit (ABE) and kick- BAUX KS start enable bit (KSE) must be set the kickstart function is used, and the KS pin must be pulled up to the V KS pin can be used as an interrupt input ...
Page 6
... Calendar and Alarm User Ram 114 Bytes Extended RAM Addr/ DS1685/DS1687 Data Registers Extended Control/ Status Registers 64-Bit Serial Num ber Century Counter RTC Address -2 RTC Address - DS1685/DS1687 3V/5V Real-Time Clocks Divide by 64 Square SQW W ave Generator IRQ IR Q Generator Registers ...
Page 7
... Registers X2 X1 NOTE: AVOID ROUTING SIGNAL LINES IN THE CROSSHATCHED AREA (UPPER LEFT QUADRANT) OF THE PACKAGE X2 UNLESS THERE IS A GROUND PLANE BETWEEN THE SIGNAL LINE AND THE DEVICE PACKAGE. GND DS1685/DS1687 3V/5V Real-Time Clocks TYP MAX UNITS 32.768 kHz 50 kΩ 6, 12.5 pF ...
Page 8
... A). This time period allows the system to stabilize after power is applied. If the oscillator is not enabled, the oscillator enable bit will be enabled on power up, and the device becomes immediately accessible. The DS1685/DS1687 is available in either device. The 5V device is fully accessible and data can be written and read only when V falls below V , read and writes are inhibited ...
Page 9
... Date 0 10 Month DV1 DV0 RS3 RS2 AIE UIE SQWE Century 10 Date DS1685/DS1687 3V/5V Real-Time Clocks BIT 1 BIT 0 FUNCTION Seconds Seconds Alarm Minutes Minutes Alarm Hours Hours Hours Hours Alarm Day Day Date Date Month Month Year Year RS1 RS0 Control ...
Page 10
... Date 0 0 Year DV1 DV0 RS3 RS2 AIE UIE SQWE Century 10 Date DS1685/DS1687 3V/5V Real-Time Clocks BIT 1 BIT 0 FUNCTION Seconds Seconds Alarm Minutes Minutes Alarm Hours Hours Hours Hours Alarm Day Day Date Month Month Year RS1 RS0 Control 24/12 ...
Page 11
... Enable both at the same time and the same rate Enable neither. Table 3 lists the periodic interrupt rates and the square-wave frequencies that can be chosen with the RS bits. BIT 5 BIT 4 BIT 3 DV1 DV0 RS3 DS1685/DS1687 3V/5V Real-Time Clocks LSB BIT 2 BIT 1 BIT 0 RS2 RS1 RS0 ...
Page 12
... When the AIE bit is set to 0, the AF bit does not initiate the IRQ signal. The internal functions of the DS1685/DS1687 do not affect the AIE bit. UIE – The update-ended interrupt-enable (UIE) bit is a read/write bit that enables the update-end flag (UF) bit in Register C to assert IRQ. The SET bit going high clears the UIE bit. SQWE – ...
Page 13
... BIT 6, BIT 5, BIT 4, BIT 3, BIT 2, BIT 1, BIT 0 – The remaining bits of Register D are not usable. They cannot be written and when read will always read 0. BIT 4 BIT BIT 5 BIT 4 BIT DS1685/DS1687 3V/5V Real-Time Clocks LSB BIT 2 BIT 1 BIT LSB BIT 2 BIT 1 BIT pin or the ...
Page 14
... The IRQF bit in Register whenever the IRQ pin is being driven low as a result of one of the six possible active sources. Therefore, determination that the DS1685/DS1687 initiated an interrupt is accomplished by reading Register C and finding IRQF = 1. IRQF remains set until all enabled interrupt flag bits are cleared to 0 ...
Page 15
... DS1287. Any other bit combination for DV2 and DV1 keeps the oscillator off. OSCILLATOR CONTROL BITS When the DS1687 is shipped from the factory, the internal oscillator is turned off. This feature prevents the lithium energy cell from being used until it is installed in a system. A pattern of 01X in bits 4 through 6 of Register A turns the oscillator on and enables the countdown chain ...
Page 16
... ensure that data is not read during the update cycle. PI BUC DS1685/DS1687 3V/5V Real-Time Clocks SQW OUTPUT FREQUENCY None 256Hz 128Hz 8.192kHz 4.096kHz 2.048kHz 1.024kHz 512Hz 256Hz 128Hz 64Hz 32Hz 16Hz 8Hz 4Hz 2Hz 32.768kHz ...
Page 17
... PF EXTENDED FUNCTIONS The extended functions provided by the DS1685/DS1687 that are new to the RAMified RTC family are accessed by a software-controlled bank-switching scheme, as illustrated in Figure 5. In bank 0, the clock/calendar registers and 50 bytes of user RAM are in the same locations as for the DS1287 result, existing routines implemented within BIOS, DOS, or application software packages can gain access to the DS1685/DS1687 clock registers with no changes ...
Page 18
... Figure 5. DS1685/DS1687 Register Map and Extended Register Bank Definition BANK 0 DV0 MSB = 0 00 TIMEKEEPING AND CONTROL BYTES-USER RAM 3F 64 BYTES-USER RAM 7F When bank 1 is selected, the clock/calendar registers and the original 50 bytes of user RAM still appear as bank 0. However, the registers that provide control and status for the extended functions are accessed in place of the additional 64 bytes of user RAM ...
Page 19
... KS pin, without operating voltage applied to the V system power can be applied upon such events as a key closure or modem-ring detect signal. In order to use either the wake-up or the kickstart features, the DS1685/DS1687 must have an auxiliary battery connected to the V pin and the oscillator must be running, and the countdown chain must not be in reset (Register A DV2, DV1, BAUX DV0 = 01X) ...
Page 20
... At the beginning of Interval 3, the system processor has begun code execution and clears the interrupt condition of WF and/ writing 0’s to both of these control bits. As long as no other interrupt within the DS1685/DS1687 is pending, the IRQ line is taken inactive once these bits are reset. Execution of the application software can proceed. ...
Page 21
... Two extended control registers are provided to supply controls and status information for the extended features offered by the DS1685/DS1687. These are designated as extended control registers 4A and 4B and are located in register bank 1, locations 04AH and 04BH, respectively. The functions of the bits within these registers are described as follows ...
Page 22
... CS – Crystal Select Bit. When CS is set the oscillator is configured for operation with a crystal that has a 6pF specified load capacitance. When the oscillator is configured for a 12.5pF crystal disabled in the DS1687 EDIP and should be set RCE – RAM Clear-Enable bit. When set this bit enables a low level on RCLR to clear all 242 bytes of user RAM. When RCE = 0, RCLR and the RAM clear function are disabled. PRS – ...
Page 23
... RTC address 4Eh is latched and the address from “1” is pushed to location “4Eh,” “RTC Address-2” while 0Ah is pushed to the “RTC Address-1” location. The data in this register, 4Eh, is the RTC address lost due to the SMI DS1685/DS1687 3V/5V Real-Time Clocks 4 ...
Page 24
... Input Logic 1 PWR Pullup Voltage IRQ Input Logic 0 Battery Voltage (-5) Auxiliary Battery Voltage (-3) SYMBOL MIN TYP 4.5 5 2.7 3 PUPWR V -0 2.5 BAT 2.5 V BAUX 2 DS1685/DS1687 3V/5V Real-Time Clocks MAX UNITS NOTES 5 0.2 CC 0.6 V 3.7 V 5 ...
Page 25
... A A SYMBOL MIN I CC1 I CC2 BATLKG OLPWR I OLIRQ = -40C to +85C.) SYMBOL MIN I BAT1 I BAT2 DS1685/DS1687 3V/5V Real-Time Clocks TYP MAX UNITS 0.5 2 A +1 0.4 V 4.37 4.5 V 2.6 2 BAT V V BAUX 10 100 nA 2.1 mA 0.8 ...
Page 26
... Input Pulse Rise and Fall Times: 5ns = -40°C to +85°C) A SYMBOL MIN TYP t 260 CYC PW 100 RWL PW 100 RWH DHR t 0 DHW t 30 ASL t 15 AHL t 30 ASD PW 80 ASH t 30 ASED t 20 DDR t 60 DSW t IRD DS1685/DS1687 3V/5V Real-Time Clocks MAX UNITS NOTES ...
Page 27
... Input Pulse Rise and Fall Times: 5ns = -40°C to 85°C.) A SYMBOL MIN TYP t 195 CYC PW 75 RWL PW 75 RWH DHR t 0 DHW t 30 ASL t 15 AHL t 25 ASD PW 40 ASH t 30 ASED t 20 DDR t 60 DSW t IRD DS1685/DS1687 3V/5V Real-Time Clocks MAX UNITS NOTES ...
Page 28
... DS1685/DS1667 BUS TIMING FOR READ CYCLE TO RTC AND RTC REGISTERS DS1685/DS1687 BUS TIMING FOR WRITE CYCLE TO RTC AND RTC REGISTERS DS1685/DS1687 3V/5V Real-Time Clocks ...
Page 29
... V 2. 2.7V V 2. SYMBOL MIN OUT SYMBOL MIN TYP t 2 KSPW t 2 POTO DS1685/DS1687 3V/5V Real-Time Clocks TYP MAX UNITS 0 ns 150 ms s s s years TYP MAX UNITS 0 ns 150 ms s s years TYP MAX UNITS ...
Page 30
... POWER-UP CONDITION—3V CS 2.6V 2. POWER FAIL POWER-DOWN CONDITION— POWER FAIL REC 2. 2.7V 2.6V 2. DS1685/DS1687 3V/5V Real-Time Clocks ...
Page 31
... POWER-UP CONDITION—5V CS 4.5V 4.25V 4. POWER FAIL POWER-DOWN CONDITION— DS1685/DS1687 3V/5V Real-Time Clocks REC 4.5V FB 4.25V 4.0V 3. ...
Page 32
... V SW Note 9: The DS1687 keeps time to an accuracy of ±1 minute per month at 25°C during data retention time for the period of t Note 10 the amount of time that the internal battery can power the internal oscillator and internal registers of the DS1687 DR at 25° ...
Page 33
... RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE 24 PDIP 28 PLCC 24 TSSOP EDIP DS1685/DS1687 3V/5V Real-Time Clocks PACKAGE CODE P24+3 Q28+4 U24+1 W24+7 MDP24 DOCUMENT NO ...
Page 34
... Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time Maxim is a registered trademark of Maxim Integrated Products, Inc. The Dallas logo is a registered trademark of Maxim Integrated Products, Inc. DS1685/DS1687 3V/5V Real-Time Clocks DESCRIPTION © 2010 Maxim Integrated Products ...