DS1742-70 Maxim Integrated Products, DS1742-70 Datasheet - Page 5

• Manufacturer Part Number: DS1742-70
• Description: IC RTC RAM Y2K 5V 70NS 24-EDIP
• Manufacturer: Maxim Integrated Products
• Type: Clock/Calendar/NVSRAM/Y2Kr

Specifications of DS1742-70

• Memory Size: 16K (2K x 8)
• Time Format: HH:MM:SS (24 hr)
• Date Format: YY-MM-DD-dd
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 24-DIP (600 mil) Module
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

RETRIEVING DATA FROM RAM OR CLOCK
The DS1742 is in the read mode whenever
(chip enable) is low. The device architecture allows ripple-through access to any of the address locations
in the NV SRAM. Valid data will be available at the DQ pins within t
stable, providing that the
states are not met, valid data will be available at the latter of chip enable access (t
access time (t
outputs are activated before t
inputs are changed while
time (t
WRITING DATA TO RAM OR CLOCK
The DS1742 is in the write mode whenever
referenced to the latter occurring transition of
the cycle.
write cycle. Data in must be valid t
typical application, the
that care is taken with the data bus to avoid bus contention. If
the data bus can become active with read data defined by the address inputs. A low transition on
then disable the outputs t
DATA RETENTION MODE
The 5V device is fully accessible and data can be written or read only when V
However, when V
internal clock registers and SRAM are blocked from any access. When V
point V
operation and SRAM data are maintained from the battery until V
3.3V device is fully accessible and data can be written or read only when V
V
device power is switched from V
greater than Vso
below Vso
nominal levels.
CC
falls below the power fail point, V
OH
SO
) but will then go indeterminate until the next address access.
(battery supply level), device power is switched from the V
CE
.
RTC operation and SRAM data are maintained from the battery until V
OEA
or
,
). The state of the data input/output pins (DQ) is controlled by
WE
the device power is switched from V
CC
is below the power fail point, V
must return inactive for a minimum of t
OE
WEZ
CE
CE
signal will be high during a write cycle. However,
after
AA
and
and
, the data lines are driven to an intermediate state until t
OE
WE
CC
OE
DS
to the backup supply (V
access times and states are satisfied. If
goes active.
prior to the end of write and remain valid for t
remain valid, output data will remain valid for output data hold
PF
,
access to the device is inhibited. If V
OE
WE
(output enable) is low,
WE
5 of 15
and
on
CE
CE
PF
CC
,
. The addresses must be held valid throughout
are in their active state. The start of a write is
to the backup supply (V
(point at which write protection occurs) the
BAT
WR
OE
) when V
prior to the initiation of another read or
is low prior to
CC
is returned to nominal levels. The
WE
CC
AA
CC
pin to the backup battery. RTC
(write enable) is high, and
CC
after the last address input is
falls below the battery switch
CC
CE
drops below V
OE
is greater than V
or
CEA
PF
can be active provided
CC
WE
BAT
is less than Vso
OE
) or at output enable
CE
is greater than V
DH
)
AA
, and
transitioning low
CC
access times and
when V
. If the address
afterward. In a
is returned to
PF
OE
.
PF
If V
WE
CC
. If the
.
When
drops
,
PF
will
CE
the
PF
is
.