AD9975BST Analog Devices Inc, AD9975BST Datasheet - Page 17

• Manufacturer Part Number: AD9975BST
• Description: IC FRONT-END MIXED-SGNL 48-LQFP
• Manufacturer: Analog Devices Inc
• Series: TxDAC+®r

Specifications of AD9975BST

• Rohs Status: RoHS non-compliant
• Number Of Bits: 10
• Number Of Channels: 1
• Voltage - Supply, Analog: 3.3V
• Voltage - Supply, Digital: 3.3V
• Package / Case: 48-LQFP
• Power (watts): -

The serial port is operated by an internal state machine and is
dependent on the number of SCLK cycles since the last time
SENABLE went active. On every eighth rising edge of SCLK, a
byte is transferred over the SPI. During a multibyte write cycle,
this means the registers of the AD9975 are not simultaneously
updated but occur sequentially. For this reason, it is recom-
mended that single byte transfers be used when changing the
SPI configuration or performing a software reset.
REGISTER PROGRAMMING DEFINITIONS
Register 0, RESET/SPI Configuration
Bit 5: Software Reset
Setting this bit high resets the chip. The PLLs will relock to the
input clock and all registers (except Register 0x0, Bit 6) revert
to their default values. Upon completion of the reset, Bit 5 is
reset to 0.
The content of the interpolator stage is not cleared by software
or hardware resets. It is recommended to “flush” the transmit
path with zeros before transmitting data.
Bit 6: LSB/MSB First
Setting this bit high causes the serial port to send and receive
data least significant bit (LSB) first. The default low state con-
figures the serial port to send and receive data most significant
bit (MSB) first.
Bit 7: Select 4-Wire SPORT
Setting this bit high puts the serial port into a four-line mode.
The SCLK and SENABLE retain their normal functions,
SDATA becomes an input only line, and the RXBOOST/SDO
pin becomes the serial port output. When in 4-wire mode, the
data on the RXBOOST/SDO pin will change on the falling edge
of SCLK and should be sampled on the rising edge of SCLK.
Register 1, Power-Down
Bit 0: Power-Down Receive Filter and CPGA
Setting this bit high powers down and bypasses the RX LPF
and continuous time programmable gain amplifier.
Bit 1: Power-Down ADC and SPGA
Setting this bit high powers down the ADC and the switched
capacitor programmable gain amplifier (SPGA).
Bit 2: Power-Down RX Reference
Setting this bit high powers down the ADC reference. This bit
should be set if an external reference is applied.
Bit 3: Power-Down Interpolators
Setting this bit high powers down the transmit digital interpolator.
It does not clear the content of the data path.
Bit 4: Power-Down DAC
Setting this bit high powers down the transmit DAC.
Bit 5: Power-Down PLL-A
Setting this bit high powers down the on-chip phase-locked loop
that generates the transmit path clocks and the auxiliary clock
CLK-A. When powered down, the CLK-A output goes to a high
impedance state.
Register 3, Clock Source Configuration
The AD9975 contains a programmable PLL referred to as PLL-A.
The output of the PLL is used to generate the internal clocks for
the TX path and the auxiliary clock, CLK-A.
REV. 0
–17–
Bit 1,0: PLL-A Multiplier
Bits 1 and 0 determine the multiplication factor (L) for PLL-A
and the DAC sampling clock frequency, F
Bit 1,0
Bit 6: ADC Clock Source OSC IN/2
Setting Bit 6 high selects the the OSC IN clock signal divided by
2 as the ADC sampling clock source. Setting Bit 6 low selects
the OSC IN clock to be used directly as the ADC sampling
clock source. The best ADC performance is achieved by using
an external crystal or by driving the OSC IN pin with a low jitter
clock source.
Register 4, Receive Filter Selection
The AD9975 receive path has a continuous time 4-pole LPF
and a 1-pole digital HPF. The 4-pole LPF has two selectable
cutoff frequencies. Additionally, the filter can be tuned around
those two cutoff frequencies. These filters can also be bypassed
to different degrees as described below.
The continuous time 4-pole low-pass filter is automatically
calibrated to one of two selectable cutoff frequencies. The cutoff
frequency, F
frequency F
tuning target word in Register 5.
Bit 0: RX LPF Bypass
Setting this bit high bypasses the 4-pole LPF. The filter is auto-
matically powered down when this bit is set.
Bit 1: Enable 1-Pole RX LPF
The AD9975 can be configured with a 1-pole filter when the
4-pole receive low-pass filter is bypassed. The 1-pole filter is
untrimmed and subject to cutoff frequency variations of ± 20%.
Bit 2: Wideband RX LPF
This bit selects the nominal cutoff frequency of the 4-pole LPF.
Setting this bit high selects a nominal cutoff frequency of 28.8 MHz.
When the wideband filter is selected, the RX path gain is limited
to 30 dB.
Bit 3: Fast ADC Sampling
Setting this bit increases the quiescent current in the SVGA block.
This may provide some performance improvement when the ADC
sampling frequency is greater than 40 MSPS.
Bit 4: RX Digital HPF Bypass
Setting this bit high bypasses the 1-pole digital HPF that follows
the ADC. The digital filter must be bypassed for ADC sampling
above 50 MSPS.
Bit 5: RX Path DC Offset Correction
Writing a 1 to this bit triggers an immediate receive path offset
correction and reads back 0 after the completion of the offset
correction.
Bit 6: RX LPF Tuning Update in Progress
This bit indicates when receive filter calibration is in progress.
The duration of a receive filter calibration is about 500 µs.
Writing to this bit has no effect.
0,0: L = 1
0,1: L = 2
1,0: L = 4
1,1: L = 8
ADC
cutoff
F
F
cutoff high
cutoff low
, is described as a function of the ADC sampling
and can be influenced ± 15% by the RX filter
_
_
=
=
F
F
ADC
ADC
×
×
158
64
/
/
(
64
(
64
DAC
+
+
Target
. F
Target
DAC
AD9975
)
)
= L × F
CLKIN
.