CS5513-BSZ Cirrus Logic Inc, CS5513-BSZ Datasheet

IC ADC 20BIT INTERNAL OSC 8SOIC

CS5513-BSZ

Manufacturer Part Number
CS5513-BSZ
Description
IC ADC 20BIT INTERNAL OSC 8SOIC
Manufacturer
Cirrus Logic Inc
Datasheet

Specifications of CS5513-BSZ

Data Interface
Serial
Number Of Bits
20
Sampling Rate (per Second)
326
Number Of Converters
1
Power Dissipation (max)
2.7mW
Voltage Supply Source
Dual ±
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
8-SOIC (0.200", 5.30mm Width)
Resolution (bits)
20bit
Sampling Rate
100SPS
Input Channel Type
Differential
Supply Voltage Range - Analog
4.75V To 5.25V
Supply Current
385µA
Digital Ic Case Style
SOIC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
598-1707

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CS5513-BSZ
Quantity:
200
Part Number:
CS5513-BSZ
Manufacturer:
CIRRUS
Quantity:
20 000
Part Number:
CS5513-BSZR
Manufacturer:
CIRRUS LOGIC/凌云
Quantity:
22
Features
http://www.cirrus.com
Delta-sigma Analog-to-digital Converter
– Linearity Error: 0.0015% FS
– Noise-free Resolution: Up to 17 Bits
Differential Bipolar Analog Inputs
V
50/60 Hz Simultaneous Rejection
(CS5510/12)
16 to 326 Sps Output Word Rate
On-chip Oscillator (CS5511/13)
Power Supply Configurations:
– V+ = 5 V, V- = 0 V
– Multiple Dual-supply Arrangements
Low Power Consumption
– Normal Mode, 2.5 mW
– Sleep Mode, 10 μW
Low-cost, Compact, 8-pin Package
Lead-free Device Package Options
VREF
AIN+
REF
AIN-
Input Range from 250 mV to 5 V
~0.8X
1X
16-bit and 20-bit, 8-pin
V+
V-
Delta-sigma
Differential
Modulator
4th-order
Copyright  Cirrus Logic, Inc. 2009
(All Rights Reserved)
(CS5511/13 only)
Oscillator
General Description
The CS5510/11/12/13 are low-cost, easy-to-use, ΔΣ an-
alog-to-digital converters (ADCs) which use charge-
balance techniques to achieve 16-bit (CS5510/11) and
20-bit (CS5512/13) performance. The ADCs are avail-
able in a space-efficient, 8-pin SOIC package and are
optimized for measuring signals in weigh scale, process
control, and other industrial applications.
To accommodate these applications, the ADCs include
a fourth-order ΔΣ modulator and a digital filter. When
configured with an external master clock of 32.768 kHz,
the filter in the CS5510/12 provides better than 80 dB of
simultaneous 50 and 60 Hz line rejection, and outputs
conversion words at 53.5 Sps. The CS5511/13 include
an on-chip oscillator which eliminates the need for an ex-
ternal clock source.
Low-power, flexible supply configurations, compact pi-
nout, and ease of use make these products ideal
solutions for cost-conscience and space-constrained
applications.
ORDERING INFORMATION
See
Digital Filter
page
ΔΣ
23.
Clock
Gen.
CS5510/11/12/13
ADCs
(CS5510/12 only)
Control
Output
Logic
SDO
SCLK
CS
DS337F4
JUL ‘09

Related parts for CS5513-BSZ

CS5513-BSZ Summary of contents

Page 1

Features  Delta-sigma Analog-to-digital Converter – Linearity Error: 0.0015% FS – Noise-free Resolution Bits  Differential Bipolar Analog Inputs  V Input Range from 250 REF  50/60 Hz ...

Page 2

TABLE OF CONTENTS 1. CHARACTERISTICS AND SPECIFICATIONS ........................................................................ 4 ANALOG CHARACTERISTICS ................................................................................................ 4 DIGITAL CHARACTERISTICS ................................................................................................. 5 DYNAMIC CHARACTERISTICS .............................................................................................. 6 ABSOLUTE MAXIMUM RATINGS ........................................................................................... 6 SWITCHING CHARACTERISTICS - CS5510/12 ..................................................................... 7 SWITCHING CHARACTERISTICS - CS5511/13 ..................................................................... 8 2. GENERAL ...

Page 3

... Figure 16. Data Word Timing for the CS5510............................................................................... 16 Figure 17. Data Word Timing for the CS5511............................................................................... 17 Figure 18. Data Word Timing for the CS5512............................................................................... 17 Figure 19. Data Word Timing for the CS5513............................................................................... 17 Figure 20. Digital Filter Response................................................................................................. 19 LIST OF TABLES Table 1. CS5512/13 Output Conversion Data Register Description (Flags + 20 bits). ................. 18 Table 2 ...

Page 4

CHARACTERISTICS AND SPECIFICATIONS ANALOG CHARACTERISTICS (T = 25° ±5 VREF = 2.5 V (relative to V-); A CS5510/12, SCLK = 32.768 kHz; CS5511/13, f CS5510/12; OWR = 107 Sps ± ...

Page 5

... SDO. The voltage specified for SDO is relative to CS Figure 11 for more details. DS337F4 (Continued) (Note 8) 0.250 {(V+) - (V-)} (Note 9) CS5510 CS5511 CS5512 CS5513 CS5510 CS5511 CS5512 CS5513 (Note 10) CS5510 CS5511 CS5512 CS5513 (Note 11) and I may not always be the same value Symbol V CS and SCLK (Note 13 SCLK (Note 14 SDO 5.0mA ...

Page 6

DYNAMIC CHARACTERISTICS Parameter Modulator Sampling Frequency Output Word Rate Filter Settling Time to 1/2 LSB (Full Scale Step) ABSOLUTE MAXIMUM RATINGS ( (See Note 15.) Parameter DC Power Supplies Input Current, Any Pin Except Supplies Output Current ...

Page 7

SWITCHING CHARACTERISTICS - CS5510/ 25° ±5 Input Levels: Logic Logic Parameter Master Clock Timing Master Clock Frequency (CS5510) Master Clock ...

Page 8

SWITCHING CHARACTERISTICS - CS5511/ 25° ±5 Input Levels: Logic Logic Parameter Internal Oscillator Timing Internal Oscillator Frequency Internal Oscillator Drift ...

Page 9

t11 Figure 1. SDO Read Timing CS5510/12 (Not to Scale t11 Figure 2. SDO ...

Page 10

GENERAL DESCRIPTION The CS5510/11/12/13 are low-cost, easy-to-use, ΔΣ analog-to-digital converters (ADCs) which use charge balance techniques to achieve 16-bit (CS5510/11) and 20-bit (CS5512/13) perfor- mance. The ADCs are available in a space-effi- cient, 8-pin, SOIC package and are optimized ...

Page 11

CS5512/13. The CS5510/11 follow the same curve, but are limited to 16 bits of resolution. Note that the reference voltage should not be estab- lished prior to having the supply voltages on the V+ and V- pins. 2.2.1 Voltage Reference ...

Page 12

V Supply Differential Input (± 80% VREF) Common Mode = Figure 6. CS5510/11/12/13 Configured with a +5.0 V Analog Supply. +2.5 V Supply Differential Input (± 80% VREF) Common Mode = -2.5 V ...

Page 13

V/+3.0V Supply Differential Input (± 80% VREF) Common Mode = -1.7 V/-2.0V Supply Figure 8. CS5510/11/12/13 Configured with V+ = +3.3 V and +3.0 V and V- = -2.0 ...

Page 14

CS defines the logic-low level for Low the digital interface. Figures 9 and 10 illustrate the threshold levels of the CS5510/11/12/13 serial in- terface (CS, SCLK, and SDO). To accommodate opto-isolators, the SCLK input is designed with a ...

Page 15

VD Ω 32.768 kHz 47 pF Figure 12. External (CMOS Compatible) Clock CS5511/13 and oscillates at 64 kHz ±32 kHz. The output word rate (OWR) for the CS5511/13 is de- rived from ...

Page 16

Reading Conversions - CS5510/12 After power-up, the CS5510/12 will begin convert- ing once a clock source is applied to the SCLK pin. When a conversion has completed, and there is new data in the output register, the SDO line ...

Page 17

... Figure 18. Data Word Timing for the CS5512 Figure 19. Data Word Timing for the CS5513. DS337F4 20 bits are the conversion data, which is output MSB first (Table 1). Bits D22-D21 are the two flag bits. The OF (Over- range Flag) bit is set to a logic 1 any time the input signal is more positive than positive full scale, or more negative than negative full scale ...

Page 18

Bipolar Input Voltage >(VFS-1.5 LSB) VFS-1.5 LSB -0.5 LSB -VFS+0.5 LSB Note: VFS in the table equals the voltage between AIN+ and AIN-. See text about error flags under overrange conditions. cessively overranged. If the OD bit is set, the ...

Page 19

Frequency Rejection Frequency (Hz) (dB) (Hz Table 4. Digital Filter Response at 32.768 kHz. ...

Page 20

... This num- ber can then be used as the zero point for any sub- sequent conversion words. In the 20-bit devices (CS5512 and CS5513), multiple conversions can be averaged to arrive at a more accurate offset val- ue. In the 16-bit devices (CS5510 and CS5511), ...

Page 21

PIN DESCRIPTIONS VREF AIN+ Control Pins and Serial Data I Chip Select, Pin dual function pin, which determines the state of SDO, as well as the digital logic-low output level. When CS is ...

Page 22

SPECIFICATION DEFINITIONS Linearity Error The deviation of a code from a straight line which connects the two end points of the A/D Converter transfer function. One end point is located 1/2 LSB below the first code transition and the ...

Page 23

... Internal CS5512-BSZ External CS5513-BSZ Internal 6. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION Model Number CS5510-ASZ CS5511-ASZ CS5512-BSZ CS5513-BSZ * MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020. DS337F4 Resolution Linearity Error (Max) Temperature Range ±0.003% 16 Bits ±0.0015% 20 Bits Peak Reflow Temp MSL Rating* 260 °C ...

Page 24

PACKAGE DIMENSIONS 8L SOIC (208 MIL BODY) PACKAGE DRAWING 1 b SEATING PLANE e DIM MIN A 0.076 A1 0.004 b 0.013 C 0.006 D 0.206 E 0.204 e 0.040 H 0.302 L 0.019 ∝ 0° ...

Page 25

REVISION HISTORY Revision Date F2 MAR 2005 Added lead-free (Pb) device ordering information. F3 AUG 2005 Updated lead-free (Pb) device ordering information. Added MSL data. F4 JUL 2009 Removed devices containing lead (Pb) from ordering information. DS337F4 CS5510/11/12/13 Changes ...

Page 26

Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to you go to IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in ...

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