CS5530-ISZ Cirrus Logic Inc, CS5530-ISZ Datasheet

IC ADC 24BIT 1CH W/LNA 20SSOP

CS5530-ISZ

Manufacturer Part Number
CS5530-ISZ
Description
IC ADC 24BIT 1CH W/LNA 20SSOP
Manufacturer
Cirrus Logic Inc
Datasheet

Specifications of CS5530-ISZ

Number Of Converters
1
Package / Case
20-SSOP
Number Of Bits
24
Sampling Rate (per Second)
3.84k
Data Interface
Serial
Power Dissipation (max)
45mW
Voltage Supply Source
Analog and Digital, Dual ±
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Number Of Adc Inputs
1
Architecture
Delta-Sigma
Conversion Rate
6.25 SPs to 3840 SPs
Resolution
24 bit
Input Type
Voltage
Interface Type
Serial (3-Wire)
Voltage Reference
2.5 V
Maximum Power Dissipation
500 mW
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1158 - BOARD EVAL FOR CS5530
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
598-1283-5

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Features
http://www.cirrus.com
Chopper-stabilized Instrumentation
Amplifier, 64X
Digital Gain Scaling up to 40x
Delta-sigma Analog-to-digital Converter
Scalable V
Simple Three-wire Serial Interface
Onboard Offset and Gain Calibration
Registers
Selectable Word Rates: 6.25 to 3,840 Sps
Selectable 50 or 60 Hz Rejection
Power Supply Configurations
• 12 nV/√Hz @ 0.1 Hz (No 1/f noise)
• 1200 pA Input Current
• Linearity Error: 0.0015% FS
• Noise Free Resolution: Up to 19 bits
• SPI™ and Microwire™ Compatible
• Schmitt-trigger on Serial Clock (SCLK)
• VA+ = +5 V; VA- = 0 V; VD+ = +3 V to +5 V
• VA+ = +2.5 V; VA- = -2.5 V; VD+ = +3 V to +5 V
• VA+ = +3 V; VA- = -3 V; VD+ = +3 V
AIN1+
AIN1-
24-bit ADC
& Description
REF
VA+
VA-
Input: Up to Analog Supply
C1
64X
A0
C2
LATCH
with
A1
Copyright  Cirrus Logic, Inc. 2009
VREF+
DIFFERENTIAL
4
MODULATOR
TH
Ultra-low-noise Amplifier
ORDER ΔΣ
(All Rights Reserved)
VREF-
General Description
The CS5530 is a highly integrated ΔΣ Analog-to-Digital
Converter (ADC) which uses charge-balance techniques
to achieve 24-bit performance. The ADC is optimized for
measuring low-level unipolar or bipolar signals in weigh
scale,
applications.
To accommodate these applications, the ADC includes
a very-low-noise, chopper-stabilized instrumentation
amplifier (12 nV/√Hz @ 0.1 Hz) with a gain of 64X. This
device also includes a fourth-order ΔΣ modulator fol-
lowed by a digital filter which provides twenty selectable
output word rates of 6.25, 7.5, 12.5, 15, 25, 30, 50, 60, 100,
120, 200, 240, 400, 480, 800, 960, 1600, 1920, 3200, and
3840 Sps (MCLK = 4.9152 MHz).
To ease communication between the ADC and a micro-
controller, the converter includes a simple three-wire se-
rial interface which is SPI and Microwire compatible with
a Schmitt-trigger input on the serial clock (SCLK).
High dynamic range, programmable output rates, and
flexible power supply options make this device an ideal
solution
applications.
ORDERING INFORMATION
See page 35.
OSC1
GENERATOR
PROGRAMMABLE
SINC FIR FILTER
CLOCK
process
for
OSC2
weigh
VD+
control,
SRAM/CONTROL
CALIBRATION
scale
INTERFACE
LOGIC
SERIAL
scientific,
and
CS5530
DGND
process
and
CS
SDI
SDO
SCLK
DS742F3
NOV ‘09
medical
control

Related parts for CS5530-ISZ

CS5530-ISZ Summary of contents

Page 1

... LATCH VA- A0 http://www.cirrus.com Ultra-low-noise Amplifier with General Description The CS5530 is a highly integrated ΔΣ Analog-to-Digital Converter (ADC) which uses charge-balance techniques to achieve 24-bit performance. The ADC is optimized for measuring low-level unipolar or bipolar signals in weigh scale, process applications. To accommodate these applications, the ADC includes a very-low-noise, chopper-stabilized instrumentation amplifier (12 nV/√ ...

Page 2

... PCB Layout ............................................................................................................ 31 3. PIN DESCRIPTIONS ...................................................................................................... 32 Clock Generator ......................................................................................................32 Control Pins and Serial Data I/O .............................................................................32 Measurement and Reference Inputs ......................................................................33 Power Supply Connections .....................................................................................33 4. SPECIFICATION DEFINITIONS ..................................................................................... 33 5. PACKAGE DRAWINGS .................................................................................................. 34 6. ORDERING INFORMATION .......................................................................................... 35 7. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION .................... 35 2 CS5530 TABLE OF CONTENTS DS742F3 ...

Page 3

... Figure 15. 120 Sps Filter Phase Plot to 120 Hz ...................................................................... 27 Figure 16. Z-Transforms of Digital Filters................................................................................ 27 Figure 17. On-chip Oscillator Model........................................................................................ 28 Figure 18. CS5530 Configured with a Single +5 V Supply ..................................................... 29 Figure 19. CS5530 Configured with ±2.5 V Analog Supplies.................................................. 29 Figure 20. CS5530 Configured with ±3 V Analog Supplies..................................................... 30 Table 1. Conversion Timing for Single Mode .......................................................................... 24 Table 2 ...

Page 4

... This specification applies to the device only and does not include any effects by external parasitic thermocouples. 4. Drift over specified temperature range after calibration at power- °C. 4 CS5530-CS Min Typ ±0.0015 - 24 - ±16 - ±32 - (Notes 3 and ±8 - ±16 - (Note CS5530 Max Unit ±0.003 %FS - Bits ±32 LSB 24 ±64 LSB 24 - nV/°C ±31 ppm ±62 ppm - ppm/°C DS742F3 ...

Page 5

... Input current on VREF+ or VREF- may increase to 250 nA if operated within VA+ or VA-. This is due to the rough charge buffer being saturated under these conditions. DS742F3 (Continued) Bipolar/Unipolar Mode (VA-) + 1 (VREF+) - (VREF-) (Note 50 Bipolar/Unipolar Mode Bipolar Mode Unipolar Mode CS5530 Min Typ Max Unit - (VA+) - 1.6 - 1200 - - 1 - pA/√Hz ...

Page 6

... Sleep DC Positive Supplies DC Negative Supply (See Notes 9 and 10 Filter Frequency (Hz) 1.94 3.88 7.75 15 122 230 390 780 CS5530-CS Max Min Typ - 6 0.6 1.0 - (Note 500 (Note 8) - 115 - 115 Noise (nV Noise-free Bits 115 16 163 15 229 15 344 13 1390 CS5530 Unit µ rms DS742F3 ...

Page 7

... Symbol All Pins Except SCLK V IH SCLK All Pins Except SCLK V IL SCLK = -1 out OH SDO -5.0 mA out = 1 out OL SDO 5.0 mA out out CS5530 Min Typ Max 0.6 VD+ - VD+ (VD+) - 0.45 - VD+ 0.0 - 0.8 0.0 0.6 (VA (VD (VA-) + 0.4 0.4 - ±1 ± ±10 - ...

Page 8

... Positive Digital VD+ Positive Analog VA+ Negative Analog VA- (Notes 18 and 19 OUT (Note 20) PDN VREF pins V INR AIN Pins V INA V IND T T stg CS5530 Ratio f MCLK/ 1/OWR 5/OWR + 3/OWR s sinc5 t 5/OWR s refers to the 3200 Sps (FRS = 1) or 3840 Sps Min Typ Max -0.3 - +6.0 -0 ...

Page 9

... MCLK (Note 22) t rise SCLK Any Digital Output (Note 22) t fall SCLK Any Digital Output (Note 23) t ost SCLK Pulse Width High t 1 Pulse Width Low CS5530 Min Typ Max Unit 1 4.9152 5 MHz 1.0 µ 100 µ 1.0 µ 100 µ ...

Page 10

... Figure 1. SDI Write Timing (Not to Scale Figure 2. SDO Read Timing (Not to Scale) CS5530 DS742F3 ...

Page 11

... SPI and Mi- crowire compatible with a Schmitt-trigger input on the serial clock (SCLK). 2.1 Analog Input Figure 3 illustrates a block diagram of the CS5530. The front end includes a chopper-stabilized instru- mentation amplifier with a gain of 64X. 1000 Ω AIN+ ...

Page 12

... Frequency (Hz) Figure 5. Measured Voltage Noise Density, 64x 2.1.3 No Offset DAC An offset DAC was not included in the CS5530 be- cause the high dynamic range of the converter eliminates the need for one. The offset register can be manipulated by the user to mimic the function of a DAC if desired. ...

Page 13

... The Command Register Descrip- tions section lists all valid commands. Gain Register (1 x 32) Gain (1 x 32) Figure 6. CS5530 Register Diagram CS5530 00000000(H) 00000000(H) 01000000(H) Conversion Data Register (1 x 32) ...

Page 14

... R/W (Read/Write) 0 Write configuration register. 1 Read configuration register. PERFORM CONVERSION D7(MSB (Multiple Conversions) 0 Perform a single conversion. 1 Perform continuous conversions. PERFORM SYSTEM OFFSET CALIBRATION D7(MSB PERFORM SYSTEM GAIN CALIBRATION D7(MSB SYNC1 D7(MSB Function: Part of the serial port re-initialization sequence CS5530 DS742F3 ...

Page 15

... SYNC0 D7(MSB Function: End of the serial port re-initialization sequence. NULL D7(MSB Function: This command is used to clear a port flag and keep the converter in the continuous conversion mode. DS742F3 CS5530 ...

Page 16

... Serial Port Interface The CS5530’s serial interface consists of four con- trol lines: CS, SDI, SDO, SCLK. Figure 7 details the command and data word timing. CS, Chip Select, is the control line which enables access to the serial port. If the CS pin is tied low, the port can function as a three wire interface. ...

Page 17

... The CS5530 accommodates three power consump- tion modes: normal, standby, and sleep. The default mode, “normal mode”, is entered after power is ap- plied. In this mode, the CS5530 typically consumes 35 mW. The other two modes are referred to as the power save modes. They power down most of the analog portion of the chip and stop filter convolu- tions ...

Page 18

... Unipolar/Bipolar Select The UP/BP Select bit sets the converter to measure either a unipolar or bipolar input span. 2.3.9 Open Circuit Detect When the OCD bit is set it activates a current source as a means to test for open thermocouples. CS5530 φ Fine 1 φ Coarse 2 VREF ≤ ...

Page 19

... Use the default output word rates. 1 Scale all output word rates and their corresponding filter characteristics by a factor of 5/6. NU (Not Used)[18:15] 0 Must always be logic 0. Reserved for future upgrades. DS742F3 D26 D25 D24 D23 IS NU VRS A1 A0 D10 CS5530 D22 D21 D20 D19 D18 FRS D17 ...

Page 20

... Normal mode. 1 Activate current source. NU (Not Used) [8:0] 0 Must always be logic 0. Reserved for future upgrades (FRS = 1) 100 Sps 50 Sps 25 Sps 12.5 Sps 6.25 Sps 3200 Sps 1600 Sps 800 Sps 400 Sps 200 Sps CS5530 DS742F3 ...

Page 21

... Any initial offset and gain errors in the internal circuitry of the chip will remain. 2.4.1 Calibration Registers The CS5530 converter has an offset register that is used to set the zero point of the converter’s transfer function. As shown in Offset Register section, one LSB in the offset register is 1.835007966 X 2 proportion of the input span (bipolar span is 2 times 2 ...

Page 22

... Note that access- ing the ADC’s serial port before a calibration has finished may result in the loss of synchronization between the microcontroller and the ADC, and may prematurely halt the calibration cycle. Figure 11. System Calibration of Gain CS5530 DS742F3 ...

Page 23

... DS742F3 FSCR, margin is again incorporated to accommo- date the intrinsic gain error. 2.5 Performing Conversions The CS5530 offers two distinctly different conver- sion modes. The paragraphs that follow detail the differences in the conversion modes. 2.5.1 Single Conversion Mode When the user transmits the perform single conver- ...

Page 24

... CS5530 10 (FRS = 1) clock ambigu- ± Clock Cycles Clock Cycles (First Conversion) (All Other Conversions) 89528 ± 8 40960 171448 ± 8 81920 335288 ± 8 163840 662968 ± 8 327680 1318328 ± 8 655360 2472 ± 8 1280 12728 ± ...

Page 25

... SCLK CS OSC2 Figure 12. Synchronizing Multiple ADCs The CS5530 output data conversions in binary for- mat when operating in unipolar mode and in two's complement when operating in bipolar mode. Ta- ble 3 shows the code mapping for both unipolar and bipolar modes. VFS in the tables refers to the posi- ...

Page 26

... Conversion Data Output Descriptions CS5530 (24-BIT CONVERSIONS) D31(MSB) D30 D29 D28 D27 MSB D15 D14 D13 D12 D11 Conversion Data Bits [31:8] These bits depict the latest output conversion. OF (Over-range Flag Bit) [2] 0 Bit is clear when over-range condition has not occurred. ...

Page 27

... Digital Filter The CS5530 has a linear phase digital filter which is programmed to achieve a range of output word rates (OWRs) as stated in the Configuration Regis- ter Description section. The ADC uses a Sinc ital filter to output word rates at 3200 Sps and 3840 Sps (MCLK = 4.9152 MHz). Other output word ...

Page 28

... NOTE capacitors are on chip and should not be added externally. Figure 17. On-chip Oscillator Model 28 2.10 Power Supply Arrangements The CS5530 is designed to operate from single or dual analog supplies and a single digital supply. The following power supply connections are possi- ble VA+ = +2.5 V; VA- = -2 ...

Page 29

... V Analog Supply - Figure 18. CS5530 Configured with a Single +5 V Supply +2.5 V Analog Supply - -2.5 V Analog Supply Figure 19. CS5530 Configured with ±2.5 V Analog Supplies DS742F3 10 Ω 0.1 µ VA+ VD+ OSC2 18 VREF+ 17 VREF- 3 OSC1 CS5530 AIN1+ 2 AIN1- SDI 20 NC SDO 19 NC SCLK 7 A0 ...

Page 30

... V Analog Supply - -3 V Analog Supply Figure 20. CS5530 Configured with ±3 V Analog Supplies 30 10 Ω 0.1 µ VA+ VD+ 18 OSC2 VREF+ 17 VREF- 3 OSC1 CS5530 AIN1+ 2 AIN1- 20 SDO SCLK DGND 6 CS5530 0.1 µF Optional 9 Clock Source 4.9152 MHz Serial SDI Data 12 Interface 11 16 ...

Page 31

... ADC initializa- tion code. Next, since the CS5530 does not provide a power-on-reset function, the user must first ini- tialize the ADC to a known state. This is accom- plished by resetting the ADC’ ...

Page 32

... AIN1 CS5530 C1 VREF+ VOLTAGE REFERENCE INPUT VREF- VOLTAGE REFERENCE INPUT 4 17 VA+ DGND DIGITAL GROUND 5 16 VA- VD+ POSITIVE DIGITAL POWER CHIP SELECT SERIAL DATA INPUT SDI 8 13 OSC2 SDO SERIAL DATA OUT 9 12 OSC1 SCLK SERIAL CLOCK INPUT 10 11 CS5530 DS742F3 ...

Page 33

... When in unipolar mode (U/B bit = 1). Units are in LSBs. Bipolar Offset The deviation of the mid-scale transition (111...111 to 000...000) from the ideal (1/2 LSB below the voltage on the AIN- pin). When in bipolar mode (U/B bit = 0). Units are in LSBs. DS742F3 CS5530 33 ...

Page 34

... CS5530 1 E1 ∝ END VIEW L NOTE MILLIMETERS MAX -- 2.13 0.25 1.88 0.38 2,3 7.50 1 8.20 5.60 1 0.69 1.03 0° ...

Page 35

... Channels Linearity Error (Max) Temperature Range CS5530- CS5530-ISZ ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION Model Number Peak Reflow Temp CS5530-IS 240 °C CS5530-ISZ 260 °C DS742F3 ±0.003% -40°C to +85°C ±0.003% -40°C to +85°C MSL Rating 2 3 CS5530 Package 20-pin 0.2" Plastic SSOP 20-pin 0.2" ...

Page 36

... Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. SPI is a trademark of Motorola, Inc. Microwire is a trademark of National Semiconductor Corporation. 36 CHANGES nput Model for AIN+ and AIN- Pins (page 11) www.cirrus.com CS5530 √ Hz. . DS742F3 ...

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