ADC08D500CIYB/NOPB National Semiconductor, ADC08D500CIYB/NOPB Datasheet - Page 24

• Manufacturer Part Number: ADC08D500CIYB/NOPB
• Description: IC ADC 8BIT 500MSPS DUAL 128LQFP
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of ADC08D500CIYB/NOPB

• Number Of Bits: 8
• Sampling Rate (per Second): 500M
• Data Interface: Serial
• Number Of Converters: 2
• Power Dissipation (max): 1.78W
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-LQFP Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *ADC08D500CIYB; *ADC08D500CIYB/NOPB; ADC08D500CIYB

1.0 Functional Description
The ADC08D500 is a versatile A/D Converter with an inno-
vative architecture permitting very high speed operation. The
controls available ease the application of the device to circuit
solutions. Optimum performance requires adherence to the
provisions discussed here and in the Applications Information
Section.
While it is generally poor practice to allow an active pin to float,
pins 4, 14 and 127 of the ADC08D500 are designed to be left
floating without jeopardy. In all discussions throughout this
data sheet, whenever a function is called by allowing a pin to
float, connecting that pin to a potential of one half the V
ply voltage will have the same effect as allowing it to float.
1.1 OVERVIEW
The ADC08D500 uses a calibrated folding and interpolating
architecture that achieves over 7.5 effective bits. The use of
folding amplifiers greatly reduces the number of comparators
and power consumption. Interpolation reduces the number of
front-end amplifiers required, minimizing the load on the input
signal and further reducing power requirements. In addition
to other things, on-chip calibration reduces the INL bow often
seen with folding architectures. The result is an extremely
fast, high performance, low power converter.
The analog input signal that is within the converter's input
voltage range is digitized to eight bits at speeds of 200 MSPS
to 500 MSPS, typical. Differential input voltages below nega-
tive full-scale will cause the output word to consist of all
zeroes. Differential input voltages above positive full-scale
will cause the output word to consist of all ones. Either of
these conditions at either the "I" or "Q" input will cause the OR
(Out of Range) output to be activated. This single OR output
indicates when the output code from one or both of the chan-
nels is below negative full scale or above positive full scale.
Each of the two converters has a 1:2 demultiplexer that feeds
two LVDS output buses. The data on these buses provide an
output word rate on each bus at half the ADC sampling rate
and must be interleaved by the user to provide output words
at the full conversion rate.
The output levels may be selected to be normal or reduced.
Using reduced levels saves power but could result in erro-
neous data capture of some or all of the bits, especially at
higher sample rates and in marginally designed systems.
1.1.1 Self-Calibration
A self-calibration is performed upon power-up and can also
be invoked by the user upon command. Calibration trims the
100Ω analog input differential termination resistor and mini-
mizes full-scale error, offset error, DNL and INL, resulting in
maximizing SNR, THD, SINAD (SNDR) and ENOB. Internal
bias currents are also set with the calibration process. All of
this is true whether the calibration is performed upon power
up or is performed upon command. Running the self calibra-
tion is an important part of this chip's functionality and is
required in order to obtain adequate performance. In addition
to the requirement to be run at power-up, self calibration must
be re-run whenever the sense of the FSR pin is changed. For
best performance, we recommend that self calibration be run
20 seconds or more after application of power and whenever
the operating temperature changes significantly, according to
the particular system design requirements. See Section
2.4.2.2 for more information. Calibration can not be initiated
or run while the device is in the power-down mode. See Sec-
tion 1.7 for information on the interaction between Power
Down and Calibration.
A
sup-
23
During the calibration process, the input termination resistor
is trimmed to a value that is equal to R
resistor is located between pin 32 and ground. R
3300 Ω ±0.1%. With this value, the input termination resistor
is trimmed to be 100 Ω. Because R
proper current for the Track and Hold amplifier, for the pream-
plifiers and for the comparators, other values of R
not be used. In normal operation, calibration is performed just
after application of power and whenever a valid calibration
command is given, which is holding the CAL pin low for at
least 80 clock cycles, then hold it high for at least another 80
clock cycles. The time taken by the calibration procedure is
specified in the A.C. Characteristics Table. Holding the CAL
pin high upon power up will prevent the calibration process
from running until the CAL pin experiences the above-men-
tioned 80 clock cycles low followed by 80 clock cycles high.
CalDly (pin 127) is used to select one of two delay times after
the application of power to the start of calibration. This cali-
bration delay is 2
with CalDly low, or 2
MSPS) with CalDly high. These delay values allow the power
supply to come up and stabilize before calibration takes place.
If the PD pin is high upon power-up, the calibration delay
counter will be disabled until the PD pin is brought low. There-
fore, holding the PD pin high during power up will further delay
the start of the power-up calibration cycle. The best setting of
the CalDly pin depends upon the power-on settling time of the
power supply.
The CalRun output is high whenever the calibration proce-
dure is running. This is true whether the calibration is done at
power-up or on-command.
1.1.2 Acquiring the Input
Data is acquired at the falling edge of CLK+ (pin 18) and the
digital equivalent of that data is available at the digital outputs
13 clock cycles later for the DI and DQ output buses and 14
clock cycles later for the DId and DQd output buses. There is
an additional internal delay called t
able at the outputs. See the Timing Diagram. The AD-
C08D500 will convert as long as the clock signal is present.
The fully differential comparator design and the innovative
design of the sample-and-hold amplifier, together with self
calibration, enables a very flat SINAD/ENOB response be-
yond 500 MHz. The ADC08D500 output data signaling is
LVDS and the output format is offset binary.
1.1.3 Control Modes
Much of the user control can be accomplished with several
control pins that are provided. Examples include initiation of
the calibration cycle, power down mode and full scale range
setting. However, the ADC08D500 also provides an Extend-
ed Control mode whereby a serial interface is used to access
register-based control of several advanced features. The Ex-
tended Control mode is not intended to be enabled and
disabled dynamically. Rather, the user is expected to employ
either the normal control mode or the Extended Control mode
at all times. When the device is in the Extended Control mode,
pin-based control of several features is replaced with register-
based control and those pin-based controls are disabled.
These pins are OutV (pin 3), OutEdge/DDR (pin 4), FSR (pin
14) and CalDly/DES (pin 127). See Section 1.2 for details on
the Extended Control mode.
1.1.4 The Analog Inputs
The ADC08D500 must be driven with a differential input sig-
nal. Operation with a single-ended signal is not recommend-
ed. It is important that the inputs either be a.c. coupled to the
25
clock cycles (about 67.2 ms at 500 MSPS)
31
clock cycles (about 4.3 seconds at 500
OD
EXT
before the data is avail-
EXT
is also used to set the
/ 33. This external
www.national.com
EXT
EXT
must be
should