MAX11646EUA+ Maxim Integrated Products, MAX11646EUA+ Datasheet - Page 14

• Manufacturer Part Number: MAX11646EUA+
• Description: IC ADC 10BIT I2C 94.4KSPS 8UMAX
• Manufacturer: Maxim Integrated Products

Specifications of MAX11646EUA+

• Number Of Bits: 10
• Sampling Rate (per Second): 94.4k
• Data Interface: I²C, Serial
• Number Of Converters: 1
• Power Dissipation (max): 362mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-TSSOP, 8-MSOP (0.118", 3.00mm Width)
• Number Of Adc Inputs: 2
• Conversion Rate: 1 Ksps to 94.4 Ksps
• Resolution: 10 bit
• Input Type: Single-Ended
• Interface Type: I2C
• Snr: 60 dB
• Voltage Reference: Internal 4.096 V
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Maximum Power Dissipation: 362 mW
• Maximum Operating Temperature: + 85 C
• Input Voltage: 4.5 V to 5.5 V
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Low-Power, 1-/2-Channel, I
in Ultra-Tiny 1.9mm x 2.2mm Package
A write cycle begins with the bus master issuing a
START condition followed by 7 address bits (Figure 7)
and a write bit (R/W = 0). If the address byte is success-
fully received, the MAX11646/MAX11647 (slave) issue
an acknowledge. The master then writes to the slave.
The slave recognizes the received byte as the setup
byte (Table 1) if the most significant bit (MSB) is 1. If the
MSB is 0, the slave recognizes that byte as the configu-
Figure 9. Write Cycle
Table 1. Setup Byte Format
14
(MSB)
______________________________________________________________________________________
BIT 7
REG
BIT
7
6
5
4
3
2
1
0
Configuration/Setup Bytes (Write Cycle)
BIP/UNI
NAME
BIT 6
SEL2
SEL2
SEL1
SEL0
REG
CLK
RST
A. 1-BYTE WRITE CYCLE
B. 2-BYTE WRITE CYCLE
1
S
1
S
X
SLAVE ADDRESS
SLAVE ADDRESS
MASTER TO SLAVE
SLAVE TO MASTER
7
7
Register bit. 1 = setup byte, 0 = configuration byte (see Table 2).
Three bits select the reference voltage (Table 6). Default to 000 at power-up.
1 = external clock, 0 = internal clock. Defaulted to 0 at power-up.
1 = bipolar, 0 = unipolar. Defaulted to 0 at power-up (see the Unipolar/Bipolar section).
1 = no action, 0 = resets the configuration register to default. Setup register remains unchanged.
Don’t-care bit. This bit can be set to 1 or 0.
SETUP OR CONFIGURATION BYTE
SETUP OR CONFIGURATION BYTE
MSB DETERMINES WHETHER
MSB DETERMINES WHETHER
BIT 5
SEL1
W
W
1 1
1 1
A
A
CONFIGURATION BYTE
CONFIGURATION BYTE
SETUP OR
SETUP OR
8
8
BIT 4
SEL0
A
A
1
1
P or Sr
CONFIGURATION BYTE
ration byte (Table 2). The master can write either 1 or 2
bytes to the slave in any order (setup byte then configu-
ration byte, configuration byte then setup byte, setup
byte or configuration byte only; see Figure 9). If the
slave receives a byte successfully, it issues an acknowl-
edge. The master ends the write cycle by issuing a
STOP condition or a repeated START condition. When
operating in HS mode, a STOP condition returns the bus
into F/S mode (see the HS Mode section).
1
SETUP OR
BIT 3
CLK
2
8
DESCRIPTION
C, 10-Bit ADCs
NUMBER OF BITS
A
1
P or Sr
BIP/UNI
BIT 2
1
NUMBER OF BITS
BIT 1
RST
(LSB)
BIT 0
X