AD6644ASTZ-65 Analog Devices Inc, AD6644ASTZ-65 Datasheet - Page 16

IC ADC 14BIT 65MSPS CMOS 52-LQFP

AD6644ASTZ-65

Manufacturer Part Number
AD6644ASTZ-65
Description
IC ADC 14BIT 65MSPS CMOS 52-LQFP
Manufacturer
Analog Devices Inc
Datasheet

Specifications of AD6644ASTZ-65

Data Interface
Parallel
Number Of Bits
14
Sampling Rate (per Second)
65M
Number Of Converters
4
Power Dissipation (max)
1.3W
Voltage Supply Source
Analog and Digital
Operating Temperature
-25°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
52-LQFP
Resolution (bits)
14bit
Sampling Rate
65MSPS
Input Channel Type
Differential
Supply Voltage Range - Digital
3V To 3.6V
Supply Current
245mA
Number Of Elements
1
Resolution
14Bit
Architecture
Pipelined
Sample Rate
65MSPS
Input Polarity
Unipolar
Input Type
Voltage
Rated Input Volt
±1.1V
Differential Input
Yes
Power Supply Requirement
Analog and Digital
Single Supply Voltage (typ)
5V
Single Supply Voltage (min)
4.85V
Single Supply Voltage (max)
5.25V
Dual Supply Voltage (typ)
Not RequiredV
Dual Supply Voltage (min)
Not RequiredV
Dual Supply Voltage (max)
Not RequiredV
Power Dissipation
1.5W
Differential Linearity Error
-1LSB/1.5LSB
Integral Nonlinearity Error
±0.5LSB(Typ)
Operating Temp Range
-25C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
52
Package Type
LQFP
Input Signal Type
Differential
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

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AD6644
input matches to a 50 Ω source with a full-scale drive of
4.8 dBm. Series resistors (R
transformer should be used to isolate the transformer from the
ADC. This limits the amount of dynamic current from the
ADC flowing back into the secondary of the transformer. The
terminating resistor (R
of the transformer.
In applications where dc coupling is required, the AD8138
differential output op amp from Analog Devices can be used
to drive the AD6644 (see Figure 30). The AD8138 op amp
provides single-ended-to-differential conversion, which reduces
overall system cost and minimizes layout requirements.
Power Supplies
Care should be taken when selecting a power source. Linear
supplies are strongly recommended. Switching supplies tend to
have radiated components that may be received by the AD6644.
Each of the power supply pins should be decoupled as closely to
the package as possible using 0.1 μF chip capacitors.
The AD6644 has separate digital and analog power supply pins.
The analog supplies are denoted AV
pins are denoted DV
power supplies. This is because the fast digital output swings
can couple switching current back into the analog supplies.
Note that AV
specified for DV
digital ASICs.
V
IN
0.1µF
ANALOG INPUT
Figure 29. Transformer-Coupled Analog Input Circuit
499Ω
SIGNAL
499Ω
CC
Figure 30. DC-Coupled Analog Input Circuit
V
OCM
must be held within 5% of 5 V. The AD6644 is
CC
= 3.3 V because this is a common supply for
R
AD8138
CC
T
499Ω
5V
C
C
. AV
T
F
F
) should be placed on the primary side
499Ω
ADT4-1WT
CC
S
) on the secondary side of the
and DV
25Ω
25Ω
+
0.1µF
R
R
CC
S
S
CC
and the digital supply
should have separate
AIN
AIN
AD6644
AIN
AIN
AD6644
V
REF
DIGITAL
OUTPUTS
Rev. D | Page 16 of 24
Digital Outputs
Care must be taken when designing the data receivers for the
AD6644. It is recommended that the digital outputs drive a
series resistor (for example, 100 Ω) followed by a gate like the
74LCX574. To minimize capacitive loading, there should only
be one gate on each output pin. An example of this is shown in
the evaluation board schematic of Figure 32. The digital outputs
of the AD6644 have a constant output slew rate of 1 V/ns.
A typical CMOS gate combined with a PCB trace have a load of
approximately 10 pF. Therefore, as each bit switches, 10 mA
(10 pF × 1 V ÷ 1 ns) of dynamic current per bit flow in or out
of the device. A full-scale transition can cause up to 140 mA
(14 bits × 10 mA/bit) of current to flow through the output
stages. The series resistors should be placed as close as possible
to the AD6644 to limit the amount of current that can flow into
the output stage. These switching currents are confined between
ground and the DV
because they can appreciably add to the dynamic switching
currents of the AD6644. Note that extra capacitive loading
increases output timing and invalidates timing specifications.
Digital output timing is guaranteed with 10 pF loads.
If the analog input range is exceeded, the overrange (OVR) bit
toggles high and the digital outputs retain their respective
positive or negative full-scale values.
Table 9. Twos Complement Output Coding
AIN Level
V
V
V
Layout Information
The schematic of the evaluation board (see Figure 32) represents a
typical implementation of the AD6644. A multilayer board is
recommended to achieve the best results. It is highly recom-
mended that high quality ceramic chip capacitors be used to
decouple each supply pin to ground directly at the device. The
pinout of the AD6644 facilitates ease of use in the implementation
of high frequency, high resolution design practices. All of the
digital outputs are segregated to two sides of the chip, with the
inputs on the opposite side for isolation purposes.
Care should be taken when routing the digital output traces.
To prevent coupling through the digital outputs into the analog
portion of the AD6644, minimal capacitive loading should be
placed on these outputs. It is recommended that a fanout of
only one gate be used for all AD6644 digital outputs. The layout
of the encode circuit is equally critical. Any noise received on
this circuitry results in corruption in the digitization process
and lower overall performance. The encode clock must be
isolated from the digital outputs and the analog inputs.
REF
REF
REF
+ 0.55 V
− 0.55 V
AIN Level
V
V
V
REF
REF
REF
CC
− 0.55 V
+ 0.55 V
pin. Standard TTL gates should be avoided
Output State
Positive FS
Midscale
Negative FS
Output Code
01 1111 1111 1111
00…0/11…1
10 0000 0000 0000

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