LTC2208IUP#TRPBF Linear Technology, LTC2208IUP#TRPBF Datasheet

IC ADC 16BIT 130MSPS 64-QFN

LTC2208IUP#TRPBF

Manufacturer Part Number
LTC2208IUP#TRPBF
Description
IC ADC 16BIT 130MSPS 64-QFN
Manufacturer
Linear Technology
Datasheet

Specifications of LTC2208IUP#TRPBF

Number Of Bits
16
Sampling Rate (per Second)
130M
Data Interface
Parallel
Number Of Converters
1
Power Dissipation (max)
1.78W
Voltage Supply Source
Single Supply
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-WFQFN, Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LTC2208IUP#TRPBFLTC2208IUP
Manufacturer:
LINEAR
Quantity:
20 000
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Part Number:
LTC2208IUP#TRPBF
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Company:
Part Number:
LTC2208IUP#TRPBFLTC2208IUP-14#TRPBF
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LT
Quantity:
340
FEATURES
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APPLICATIONS
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TYPICAL APPLICATION
ANALOG
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
INPUT
Sample Rate: 130Msps
78dBFS Noise Floor
100dB SFDR
SFDR >83dB at 250MHz (1.5V
PGA Front End (2.25V
700MHz Full Power Bandwidth S/H
Optional Internal Dither
Optional Data Output Randomizer
LVDS or CMOS Outputs
Single 3.3V Supply
Power Dissipation: 1.25W
Clock Duty Cycle Stabilizer
Pin Compatible 14-Bit Version
64-Pin (9mm × 9mm) QFN Package
Telecommunications
Receivers
Cellular Base Stations
Spectrum Analysis
Imaging Systems
ATE
V
2.2μF
CM
AIN
AIN
130Msps: LTC2208 (16-Bit), LTC2208-14 (14-Bit)
+
COMMON MODE
BIAS VOLTAGE
+
CLOCK/DUTY
ENC
CONTROL
AMP
S/H
CYCLE
1.25V
+
ENC
INTERNAL ADC
P-P
GENERATOR
REFERENCE
PIPELINED
ADC CORE
16-BIT
3.3V
or 1.5V
SENSE
PGA
P-P
SHDN
P-P
Input Range)
ADC CONTROL INPUTS
SHIFT REGISTER
CORRECTION
LOGIC AND
Input Range)
DITH
MODE
LVDS
DRIVERS
OUTPUT
RAND
OV
OGND
GND
V
DESCRIPTION
DD
The LTC
designed for digitizing high frequency, wide dynamic
range signals with input frequencies up to 700MHz. The
input range of the ADC can be optimized with the PGA
front end.
The LTC2208 is perfect for demanding communications
applications, with AC performance that includes 78dBFS
Noise Floor and 100dB spurious free dynamic range
(SFDR). Ultra low jitter of 70fs
of high input frequencies with excellent noise performance.
Maximum DC specs include ±4LSB INL, ±1LSB DNL (no
missing codes).
The digital output can be either differential LVDS or
single-ended CMOS. There are two format options for the
CMOS outputs: a single bus running at the full data rate or
demultiplexed buses running at half data rate. A separate
output power supply allows the CMOS output swing to
range from 0.5V to 3.6V.
The ENC
or single-ended with a sine wave, PECL, LVDS, TTL or
CMOS inputs. An optional clock duty cycle stabilizer al-
lows high performance at full speed with a wide range of
clock duty cycles.
DD
OF
CLKOUT
D15
D0
1μF
1μF
®
0.5V TO 3.6V
2208 is a 130Msps, sampling 16-bit A/D converter
+
and ENC
CMOS
OR
LVDS
16-Bit, 130Msps ADC
1μF
1μF
2208 TA01
3.3V
inputs may be driven differentially
–130
–100
–110
–120
–10
–20
–30
–40
–50
–60
–70
–80
–90
0
0
RMS
64k Point FFT, F
10
allows undersampling
–1dB, PGA = 0
20
FREQUENCY (MHz)
LTC2208
30
IN
40
= 15.1MHz,
50
2208fc
2208 TA01b
1
60

Related parts for LTC2208IUP#TRPBF

LTC2208IUP#TRPBF Summary of contents

Page 1

... Receivers n Cellular Base Stations n Spectrum Analysis n Imaging Systems n ATE L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. TYPICAL APPLICATION 3.3V SENSE 1.25V INTERNAL ADC V CM ...

Page 2

... LTC2208CUP#PBF LTC2208CUP#TRPBF LTC2208IUP#PBF LTC2208IUP#TRPBF Consult LTC Marketing for parts specifi ed with wider operating temperature ranges. *The temperature grade is identifi label on the shipping container Consult LTC Marketing for information on non-standard lead based fi nish parts. For more information on lead free part marking, go to: For more information on tape and reel specifi ...

Page 3

ANALOG INPUT l The denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are 25°C. (Note 4) A SYMBOL PARAMETER + V – Analog Input Range ( Analog ...

Page 4

LTC2208 DYNAMIC ACCURACY otherwise specifi cations are 25° SYMBOL PARAMETER SFDR Spurious Free Dynamic Range th 4 Harmonic or Higher S/(N+D) Signal-to-Noise Plus Distortion Ratio SFDR Spurious Free Dynamic Range at –25dBFS Dither “OFF” SFDR ...

Page 5

COMMON MODE BIAS CHARACTERISTICS the full operating temperature range, otherwise specifi cations are at T PARAMETER V Output Voltage CM V Output Tempco CM V Line Regulation CM V Output Resistance CM DIGITAL INPUTS AND DIGITAL OUTPUTS full operating temperature ...

Page 6

LTC2208 POWER REQUIREMENTS range, otherwise specifi cations are SYMBOL PARAMETER V Analog Supply Voltage DD P Shutdown Power SHDN STANDARD LVDS OUTPUT MODE OV Output Supply Voltage DD I Analog Supply Current VDD I Output Supply Current ...

Page 7

ELECTRICAL CHARACTERISTICS Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values ...

Page 8

LTC2208 TIMING DIAGRAMS ANALOG INPUT – ENC + ENC DA0-DA15, OFA CLKOUTA CLKOUTB DB0-DB15, OFB ANALOG INPUT N – ENC + ENC DA0-DA15, OFA DB0-DB15, OFB CLKOUTA CLKOUTB 8 Full-Rate CMOS Output Mode Timing All Outputs are Single-Ended and Have ...

Page 9

TYPICAL PERFORMANCE CHARACTERISTICS Integral Nonlinearity (INL) vs Output Code 2 1.5 1 0.5 0 –0.5 –1 –1.5 –2 0 16384 32768 49152 65536 OUTPUT CODE 2208 G01 128k Point FFT 4.93MHz, IN –1dBFS, PGA = 0 0 –10 ...

Page 10

LTC2208 TYPICAL PERFORMANCE CHARACTERISTICS SFDR vs Input Level 15MHz, IN PGA = 0, Dither “Off” 140 130 120 110 100 –80 –70 –60 –50 –40 –30 –20 –10 ...

Page 11

TYPICAL PERFORMANCE CHARACTERISTICS SFDR vs Input Level 70.2MHz, IN PGA = 0, Dither “Off” 130 120 110 100 –80 –20 –10 –70 –60 –50 –40 –30 INPUT LEVEL (dBFS) 2208 G28 ...

Page 12

LTC2208 TYPICAL PERFORMANCE CHARACTERISTICS 64k Point FFT 250.1MHz, IN –1dBFS, PGA = 1 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 FREQUENCY (MHz) 2208 G36 64k ...

Page 13

TYPICAL PERFORMANCE CHARACTERISTICS SNR and SFDR vs Duty Cycle 110 100 90 80 SNR DCS OFF 70 SNR DCS ON SFDR DCS OFF SFDR DCS DUTY CYCLE (%) Input Offset Voltage vs Temperature, 5 Units ...

Page 14

LTC2208 PIN FUNCTIONS For CMOS Mode. Full Rate or Demultiplexed SENSE (Pin 1): Reference Mode Select and External Reference Input. Tie SENSE 2.5V bandgap reference. An external reference of 2.5V or 1.25V may be used; both reference ...

Page 15

PIN FUNCTIONS For LVDS Mode. STANDARD or LOW POWER SENSE (Pin 1): Reference Mode Select and External Reference Input. Tie SENSE 2.5V bandgap reference. An external reference of 2.5V or 1.25V may be used; both reference values ...

Page 16

LTC2208 BLOCK DIAGRAM + A IN INPUT FIRST PIPELINED S/H ADC STAGE – DITHER SIGNAL GENERATOR RANGE SELECT SENSE PGA V CM BUFFER VOLTAGE REFERENCE 16 SECOND PIPELINED THIRD PIPELINED FOURTH PIPELINED ADC STAGE ADC STAGE ADC CLOCKS ...

Page 17

OPERATION DYNAMIC PERFORMANCE Signal-to-Noise Plus Distortion Ratio The signal-to-noise plus distortion ratio [S/(N+D)] is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components at the ADC output. The output ...

Page 18

LTC2208 APPLICATIONS INFORMATION CONVERTER OPERATION The LTC2208 is a CMOS pipelined multistep converter with a front-end PGA. As shown in Figure 1, the converter has fi ve pipelined ADC stages; a sampled analog input will result in a digitized value ...

Page 19

APPLICATIONS INFORMATION input change is large, such as the change seen with input frequencies near Nyquist, then a larger charging glitch will be seen. Common Mode Bias The ADC sample-and-hold circuit requires differential drive to achieve specifi ed performance. Each ...

Page 20

LTC2208 APPLICATIONS INFORMATION Figure 4a shows transformer coupling using a transmis- sion line balun transformer. This type of transformer has much better high frequency response and balance than fl ux coupled center tap transformers. Coupling capacitors are added at the ...

Page 21

APPLICATIONS INFORMATION The internal programmable gain amplifi er provides the internal reference voltage for the ADC. This amplifi er has very stringent settling requirements and is not accessible for external use. The SENSE pin can be driven ±5% around the ...

Page 22

LTC2208 APPLICATIONS INFORMATION ENC V = 1.6V THRESHOLD 1.6V ENC 0.1μF Figure 9. Single-Ended ENC Drive, Not Recommended for Low Jitter 3.3V 3.3V MC100LVELT22 130Ω 83Ω Figure 10. ENC Drive Using a CMOS to PECL Translator Maximum ...

Page 23

APPLICATIONS INFORMATION output may be used but is not required since the ADC has a series resistor of 43Ω on chip. Lower OV voltages will also help reduce interference DD from the digital outputs DATA PREDRIVER ...

Page 24

LTC2208 APPLICATIONS INFORMATION Overfl ow Bit An overfl ow output bit (OF) indicates when the converter is over-ranged or under-ranged. In CMOS mode, a logic high on the OFA pin indicates an overfl underfl the A ...

Page 25

APPLICATIONS INFORMATION PC BOARD FPGA CLKOUT OF D15/D0 LTC2208 D14/D0 D2/D0 D1/D0 D0 Figure 14. Descrambling a Scrambled Digital Output LTC2208 + AIN ANALOG S/H INPUT AMP – AIN CLOCK/DUTY CYCLE CONTROL + ENC Figure 15. Functional Equivalent Block Diagram ...

Page 26

LTC2208 APPLICATIONS INFORMATION Grounding and Bypassing The LTC2208 requires a printed circuit board with a clean unbroken ground plane; a multilayer board with an internal ground plane is recommended. The pinout of the LTC2208 has been optimized for a fl ...

Page 27

APPLICATIONS INFORMATION Layer 1 Component Side LTC2208 Layer 2 GND Plane 2208fc 27 ...

Page 28

LTC2208 APPLICATIONS INFORMATION Layer 3 GND 28 Layer 4 GND 2208fc ...

Page 29

APPLICATIONS INFORMATION Layer 5 GND LTC2208 Layer 6 Bottom Side 2208fc 29 ...

Page 30

LTC2208 APPLICATIONS INFORMATION VC5 48 VC4 47 VC3 26 VC2 25 VC1 • • 30 VE5 VC5 37 48 VE4 VC4 36 47 ...

Page 31

... SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 6. DRAWING NOT TO SCALE Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. UP Package 64-Lead Plastic QFN (9mm × ...

Page 32

... SNR, 9mm × 9mm QFN Package DC to 3GHz, 21dBm IIP3, Integrated LO Buffer 450MHz 1dB BW, 47dB OIP3, Digital Gain Control 10.5dB to 33dB in 1.5dB/Step 4.5V to 5.25V Supply, 25dBm IIP3 at 900MHz 12.5dB, 50Ω Single-Ended RF and LO Ports www.linear.com ● 2208fc LT 0909 REV C • PRINTED IN USA © LINEAR TECHNOLOGY CORPORATION 2005 ...

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