AD7854ARS Analog Devices Inc, AD7854ARS Datasheet
AD7854ARS
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AD7854ARS Summary of contents
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FEATURES Specified for 5 Read-Only Operation AD7854–200 kSPS; AD7854L–100 kSPS System and Self-Calibration Low Power Normal Operation AD7854 AD7854L: 5 ...
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AD7854/AD7854L–SPECIFICATIONS External Reference MHz (for L Version: 1.8 MHz ( +70 C) and 1 MHz (– +85 C)); f CLKIN (AD7854L unless otherwise noted.) Specifications in () ...
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Parameter A Version POWER REQUIREMENTS AV DV +3.0/+5.5 DD Normal Mode 5.5 (1.8) 5.5 (1.8) 6 Sleep Mode With External Clock On 10 400 With External Clock Off 5 200 Normal Mode Power Dissipation 30 (10) ...
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AD7854/AD7854L 1 TIMING SPECIFICATIONS Limit MIN MAX ( Versions) Parameter 500 500 CLKIN 4 4 1.8 1 100 100 4.5 ...
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... AIN(– HBEN 13 16 DB0 DB1 14 15 Model AD7854AQ AD7854SQ AD7854AR AD7854BR AD7854ARS 3 AD7854LAQ 3 AD7854LAR 3 AD7854LARS 4 EVAL-AD7854CB EVAL-CONTROL BOARD NOTES 1 Linearity error refers to the integral linearity error Cerdip SOIC SSOP signifies the low power version. 4 This can be used as a stand-alone evaluation board or in conjunction with the EVAL-CONTROL BOARD for evaluation/demonstration purposes ...
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AD7854/AD7854L Pin Mnemonic Description CONVST 1 Convert Start. Logic input. A low to high transition on this input puts the track/hold into its hold mode and starts conversion. When this input is not used, it should be tied to DV ...
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TERMINOLOGY Integral Nonlinearity This is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function. The end- points of the transfer function are zero scale, a point 1/2 LSB below the first code transition, ...
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AD7854/AD7854L AD7854/AD7854L ON-CHIP REGISTERS The AD7854/AD7854L powers up with a set of default conditions, and the user need not ever write to the device. In this case the AD7854/AD7854L will operate as a read-only ADC. The WR pin should be ...
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CONTROL REGISTER The arrangement of the control register is shown below. The control register is a write only register and contains 14 bits of data. The control register is selected by putting two 1s in ADDR1 and ADDR0. The function ...
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AD7854/AD7854L STATUS REGISTER The arrangement of the status register is shown below. The status register is a read-only register and contains 16 bits of data. The status register is selected by writing to the control register and putting two 1s ...
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CALIBRATION REGISTERS The AD7854/AD7854L has 10 calibration registers in all, 8 for the DAC, 1 for offset and 1 for gain. Data can be written to or read from all 10 calibration registers. In self- and system calibration, the part ...
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AD7854/AD7854L START WRITE TO CONTROL REGISTER SETTING STCAL = 0, RDSLT1 = 1, RDSLT0 = 0, AND CALSLT1, CALSLT0 = 00, 01, 10, 11 CAL REGISTER POINTER IS AUTOMATICALLY RESET READ CAL REGISTER CAL REGISTER POINTER IS AUTOMATICALLY INCREMENTED LAST ...
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CIRCUIT INFORMATION The AD7854/AD7854L is a fast, 12-bit single supply A/D con- verter. The part requires an external 4 MHz/1.8 MHz master capacitors, a CONVST signal to start clock (CLKIN), two C REF conversion and power supply decoupling capacitors. The ...
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AD7854/AD7854L ANALOG INPUT The equivalent analog input circuit is shown in Figure 9. Dur- ing the acquisition interval the switches are both in the track position and the AIN(+) charges the 20 pF capacitor through the 125 Ω resistance. On ...
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Input Ranges The analog input range for the AD7854/AD7854L both the unipolar and bipolar ranges. REF The only difference between the unipolar range and the bipolar range is that in the bipolar range the ...
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AD7854/AD7854L REFERENCE SECTION For specified performance recommended that when using an external reference, this reference should be between 2.3 V and the analog supply AV . The connections for the reference DD pins are shown below. If the ...
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3.3V/5.0V 100mV pk-pk SINE WAVE ON AV –80 –82 –84 –86 –88 – INPUT FREQUENCY – kHz Figure 20. PSRR vs. Frequency POWER-DOWN OPTIONS The AD7854/AD7854L provides flexible power ...
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AD7854/AD7854L Using The Internal (On-Chip) Reference As in the case of an external reference the AD7854/AD7854L can power up from one of two conditions, power-up after the sup- plies are connected or power-up from a software power-down. When using the ...
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AD7854 FULL POWER-DOWN CLKIN = 4MHz DD 1 ON-CHIP REFERENCE 0.1 0. THROUGHPUT RATE – kSPS Figure 24. Power vs. Throughput AD7854 AD7854L FULL POWER-DOWN CLKIN = 1.8MHz DD 1 ...
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AD7854/AD7854L CALIBRATION SECTION Calibration Overview The automatic calibration that is performed on power-up ensures that the calibration options covered in this section are not required in a significant number of applications. A calibration does not have to be initiated unless ...
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Self-Calibration Timing Figure 29 shows the timing for a software full self-calibration. Here the BUSY line stays high for the full length of the self- calibration. A self-calibration is initiated by writing to the con- trol register and setting the ...
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AD7854/AD7854L System Gain and Offset Interaction The architecture of the AD7854/AD7854L leads to an interac- tion between the system offset and gain errors when a system calibration is performed. Therefore it is recommended to perform the cycle of a system ...
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PARALLEL INTERFACE Reading The timing diagram for a read cycle is shown in Figure 35. The CONVST and BUSY signals are not shown here as the read cycle may occur while a conversion is in progress or after the conversion ...
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AD7854/AD7854L MICROPROCESSOR INTERFACING The parallel port on the AD7854/AD7854L allows the device to be interfaced to microprocessors or DSP processors as a memory mapped or I/O mapped device. The CS and RD inputs are common to all memory peripheral interfacing. ...
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AD7854/AD7854L to TMS320C30 Figure 40 shows a parallel interface between the AD7854/ AD7854L and the TMS320C3x family of DSPs. The AD7854/AD7854L is interfaced to the Expansion Bus of the TMS320C3x. Two wait states are required in this interface. These can ...
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AD7854/AD7854L APPLICATION HINTS Grounding and Layout The analog and digital supplies of the AD7854/AD7854L are independent and separately pinned out to minimize coupling between the analog and digital sections of the device. The part has very good immunity to noise ...
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PAGE INDEX Topic FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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AD7854/AD7854L 0.005 (0.13) MIN 0.225 (5.72) MAX 0.200 (5.08) 0.125 (3.18) 0.0118 (0.30) 0.0040 (0.10) 0.078 (1.98) 0.068 (1.73) 0.008 (0.203) 0.002 (0.050) OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 28-Lead Cerdip (Q-28) 0.100 (2.54) MAX 28 15 0.610 ...