AD7892AR-2REEL7 Analog Devices Inc, AD7892AR-2REEL7 Datasheet - Page 10

• Manufacturer Part Number: AD7892AR-2REEL7
• Description: IC ADC 12BIT LP 500KSPS 24-SOIC
• Manufacturer: Analog Devices Inc

Specifications of AD7892AR-2REEL7

• Rohs Status: RoHS non-compliant
• Number Of Bits: 12
• Sampling Rate (per Second): 500k
• Data Interface: Serial, Parallel
• Number Of Converters: 1
• Power Dissipation (max): 90mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (0.300", 7.50mm Width)

AD7892
pulse can be applied to the CS and RD inputs to latch data out
of the AD7892 and into the gate array or ASIC. This eliminates
the logic required in the gate array or ASIC to recognize the end
of conversion and generate the read signal for the AD7892. To
obtain optimum performance from the AD7892, it is not recom-
mended to tie CS and RD permanently low as this keeps the
three-state active during conversion.
Serial Interface Mode
The AD7892 is configured for serial mode interfacing by tying
the MODE input low. It provides for a three-wire, serial link
between the AD7892 and industry-standard microprocessors,
microcontrollers and digital signal processors. SCLK and RFS
of the AD7892 are inputs, and the AD7892’s serial interface is
designed for direct interface to systems that provide a serial
clock input that is synchronized to the serial data output includ-
ing microcontrollers such as the 80C51, 87C51, 68HC11 and
68HC05 and most digital signal processors.
Figure 3 shows the timing diagram for reading from the AD7892
in the serial interface mode. RFS goes low to access data from
the AD7892. The serial clock input does not have to be con-
tinuous. The serial data can be accessed in a number of bytes.
However, RFS must remain low for the duration of the data
transfer operation. Sixteen bits of data are transmitted with four
leading zeros followed by the 12-bit conversion result starting
with the MSB. Serial data is clocked out of the device on the
rising edge of SCLK. Old data is guaranteed to be valid for 5 ns
after this edge. This is useful for high speed serial clocks where
the access time of the part would not allow sufficient set-up time
for the data to be accepted on the falling edge of the clock. In
this case, care must be taken that RFS does not go just prior to
a rising edge of SCLK. For slower serial clocks data is valid on
the falling edge of SCLK. At the end of the read operation, the
SDATA line is three-stated by a rising edge on either the SCLK
or RFS inputs, whichever occurs first. Serial data cannot be
read during conversion to avoid feedthrough problems from the
serial clock to the conversion process. For optimum perfor-
mance of the AD7892-3, a serial read should also be avoided
within 200 ns of the rising edge of CONVST to avoid feedthrough
into the track/hold during its acquisition time. The serial read
should, therefore, occur between the end of conversion (EOC
falling edge) and 200 ns prior to the next rising edge of
SDATA (O)
SCLK (I)
RFS (I)
NOTE:
I = INPUT; O = OUTPUT
t
11
t
10
FOUR LEADING ZEROS
t
12
t
13
CONVST. For the AD7892-1 and AD7892-2, a serial read
should also be avoided within 400 ns of the rising edge of
CONVST. This limits the maximum achievable throughput
rate in serial mode (assuming 20 MHz serial clock) to 400 kSPS
for the AD7892-3 and 357 kSPS for the AD7892-1 and
AD7892-2.
Analog Input Section
The AD7892 is offered as three part types allowing for four
different analog input voltage ranges. The AD7892-1 handles
either ± 5 V or ± 10 V input voltage ranges. The AD7892-2
handles a 0 V to +2.5 V input voltage range while the AD7892-3
handles an input range of ± 2.5 V.
AD7892-1
Figure 4 shows the analog input section for the AD7892-1. The
analog input range is pin-strappable (using V
or ± 10 V on the V
input range on V
15 kΩ nominal. With V
V
As a result, the V
low impedance source. The resistor attenuator stage is followed
by the high input impedance stage of the track/hold amplifier.
This resistor attenuator stage allows the input voltage to go to
± 17 V without damaging the AD7892-1.
IN1
DB11
is ± 5 V, and the input resistance on V
REF OUT/
REF IN
t
AGND
15
DB10
V
V
t
IN2
IN1
14
IN1
IN1
IN1
is ± 10 V, and the input resistance on V
and V
input. With V
IN2
2k
t
17A
IN2
13k
13k
connected to V
DB0
inputs should be driven from a
THREE-
STATE
t
16
REFERENCE
IN2
t
6.5k
3.25k
17
+2.5
connected to AGND, the
IN1
IN1
, the input range on
IN2
TO ADC
REFERENCE
CIRCUITRY
TO HIGH
IMPEDANCE
SHA INPUT
is 8 kΩ nominal.
) for either ± 5 V
IN1
is