AD7892AR-3 Analog Devices Inc, AD7892AR-3 Datasheet - Page 7

• Manufacturer Part Number: AD7892AR-3
• Description: IC ADC 12BIT LP 600KSPS 24-SOIC
• Manufacturer: Analog Devices Inc

Specifications of AD7892AR-3

• Rohs Status: RoHS non-compliant
• Number Of Bits: 12
• Sampling Rate (per Second): 600k
• Data Interface: Serial, Parallel
• Number Of Converters: 1
• Power Dissipation (max): 90mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (0.300", 7.50mm Width)

Pin
No.
16
17
18
19
20
21
22
23
24
Mnemonic
DB4/SCLK
DB3/RFS
DB2
DB1
DB0
RD
CS
EOC
CONVST
Description
Data Bit 4/Serial Clock. When the device is in its parallel mode, this pin is Data Bit 4, a three-state
TTL-compatible output. When the device is in its serial mode, this becomes the serial clock pin,
SCLK. SCLK is an input and an external serial clock must be provided at this pin to obtain serial
data from the AD7892. Serial data is clocked out from the output shift register on the rising edges
of SCLK after RFS goes low.
Data Bit 3/Receive Frame Synchronization. When the device is in its parallel mode, this pin is Data
Bit 3, a three-state TTL-compatible output. When the device is in its serial mode, this becomes the
receive frame synchronization input with RFS provided externally to obtain serial data from the
AD7892.
Data Bit 2. Three-state TTL-compatible output. This output should be left unconnected when the
device is in its serial mode.
Data Bit 1. Three-state TTL-compatible output. This output should be left unconnected when the
device is in its serial mode.
Data Bit 0 (LSB). Three-state TTL-compatible output. Output coding is two’s complement for
AD7892-1 and AD7892-3 and straight (natural) binary for AD7892-2. This output should be left
unconnected when the device is in its serial mode.
Read. Active low logic input which is used in conjunction with CS low to enable the data outputs.
Chip Select. Active low logic input which is used in conjunction with RD to enable the data outputs.
End-of-Conversion. Active low logic output indicating converter status. The end of conversion is
signified by a low going pulse on this line. The duration of this EOC pulse is nominally 100 ns.
Convert Start. Logic Input. A low-to-high transition on this input puts the track/hold into its hold
mode and starts conversion.
REF OUT/REF IN
DB11/LOW
DB10/LOW
STANDBY
MODE
AGND
DB9
DB7
V
V
V
DB8
PIN CONFIGURATION
IN2
IN1
DD
10
11
11
12
4
1
2
3
5
6
7
8
9
DIP and SOIC
(Not to Scale)
AD7892
TOP VIEW
24
23
21
20
19
18
17
16
15
14
13
22
CONVST
EOC
CS
RD
DB0 (LSB)
DB1
DB2
DB3/RFS
DB4/SCLK
DB5/SDATA
DGND
DB6
AD7892