MAX1020BETX+ Maxim Integrated Products, MAX1020BETX+ Datasheet - Page 16

• Manufacturer Part Number: MAX1020BETX+
• Description: IC ADC/DAC 10BIT 36-TQFN-EP
• Manufacturer: Maxim Integrated Products
• Type: ADC, DACr

Specifications of MAX1020BETX+

• Resolution (bits): 10 b
• Sampling Rate (per Second): 225k
• Data Interface: MICROWIRE™, QSPI™, Serial, SPI™
• Voltage Supply Source: Analog and Digital
• Voltage - Supply: 4.75 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 36-TQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
16
15, 23, 32,
MAX1020
16–19
24, 25
9–12,
1, 2
13
14
33
20
21
22
______________________________________________________________________________________
3
4
5
6
7
8
2, 15, 24, 32
MAX1022
16–19
9–12,
—
13
14
32
20
21
22
—
3
4
5
6
7
8
MAX1057/
MAX1058
12–15,
22–25
—
10
11
18
19
—
26
27
28
—
4
7
8
9
GP IOC 0, G P IOC 1 G ener al - P ur p ose I/O C 0, C 1. G P IO C 0, C 1 can si nk 4m A and sour ce 2m A.
GP IOA0, G P IOA1 General-Purpose I/O A0, A1. GPIOA0, A1 can sink and source 15mA.
OUT0–OUT7
RES_SEL
NAME
DGND
AGND
DOUT
LDAC
DV
SCLK
AV
EOC
N.C.
DIN
CS
DD
DD
Active-Low End-of-Conversion Output. Data is valid after the falling edge
of EOC.
Digital Positive-Power Input. Bypass DV
capacitor.
Digital Ground. Connect DGND to AGND.
Serial-Data Output. Data is clocked out on the falling edge of the SCLK
clock in modes 00, 01, and 10. Data is clocked out on the rising edge of
the SCLK clock in mode 11. It is high impedance when CS is high.
Serial-Clock Input. Clocks data in and out of the serial interface. (Duty
cycle must be 40% to 60%.) See Table 5 for details on programming the
clock mode.
Serial-Data Input. DIN data is latched into the serial interface on the
falling edge of SCLK.
DAC Outputs
Positive Analog Power Input. Bypass AV
capacitor.
Analog Ground
No Connection. Not internally connected.
Active-Low Load DAC. LDAC is an asynchronous active-low input that
updates the DAC outputs. Drive LDAC low to make the DAC registers
transparent.
Active-Low Chip-Select Input. When CS is low, the serial interface is
enabled. When CS is high, DOUT is high impedance.
Reset Select. Select DAC wake-up mode. Set RES_SEL low to wake up
the DAC outputs with a 100kΩ resistor to GND or set RES_SEL high to
wake up the DAC outputs with a 100kΩ resistor to V
high to power up the DAC input register to FFFh. Set RES_SEL low to
power up the DAC input register to 000h.
FUNCTION
DD
DD
to DGND with a 0.1µF
to AGND with a 0.1µF
Pin Description
REF
. Set RES_SEL