MAX1020BETX+ Maxim Integrated Products, MAX1020BETX+ Datasheet - Page 21

• Manufacturer Part Number: MAX1020BETX+
• Description: IC ADC/DAC 10BIT 36-TQFN-EP
• Manufacturer: Maxim Integrated Products
• Type: ADC, DACr

Specifications of MAX1020BETX+

• Resolution (bits): 10 b
• Sampling Rate (per Second): 225k
• Data Interface: MICROWIRE™, QSPI™, Serial, SPI™
• Voltage Supply Source: Analog and Digital
• Voltage - Supply: 4.75 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 36-TQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Address the unipolar- and bipolar-mode registers
through the setup register (bits 1 and 0). See Table 5 for
the setup register. See Figures 3 and 4 for the transfer-
function graphs. Program a pair of analog inputs for dif-
ferential operation by writing a one to the appropriate bit
of the bipolar- or unipolar-mode register. Unipolar mode
sets the differential input range from 0 to V
tive differential analog input in unipolar mode causes the
digital output code to be zero. Selecting bipolar mode
sets the differential input range to ±V
output code is binary in unipolar mode and two’s com-
plement in bipolar mode.
In single-ended mode, the MAX1020/MAX1022/
MAX1057/MAX1058 always operate in unipolar mode.
The analog inputs are internally referenced to AGND
with a full-scale input range from 0 to the selected refer-
ence voltage.
The equivalent circuit of Figure 2 shows the ADC input
architecture of the MAX1020/MAX1022/MAX1057/
MAX1058. In track mode, a positive input capacitor is
connected to AIN0–AIN15 in single-ended mode and
AIN0, AIN2, and AIN4–AIN14 (only positive inputs) in
differential mode. A negative input capacitor is con-
nected to AGND in single-ended mode or AIN1, AIN3,
and AIN5–AIN15 (only negative inputs) in differential
mode. For external T/H timing, use clock mode 01. After
the T/H enters hold mode, the difference between the
sampled positive and negative input voltages is con-
Figure 2. Equivalent Input Circuit
(SINGLE-ENDED),
(SINGLE-ENDED),
(DIFFERENTIAL)
(DIFFERENTIAL)
AIN0–AIN15
AIN4–AIN14
AIN5–AIN15
AIN0, AIN2,
AIN1, AIN3,
AGND
10-Bit, Multichannel ADCs/DACs with FIFO,
HOLD
ACQ
ACQ
______________________________________________________________________________________
Unipolar or Bipolar Conversions
AV
HOLD
DD
Temperature Sensing, and GPIO Ports
AGND
/ 2
REF1
CIN+
CIN-
DAC
Analog Input (T/H)
ACQ
REF1
/ 2. The digital
REF1.
COMPARATOR
A nega-
HOLD
verted. The input capacitance charging rate determines
the time required for the T/H to acquire an input signal.
If the input signal’s source impedance is high, the
required acquisition time lengthens.
Any source impedance below 300Ω does not signifi-
cantly affect the ADC’s AC performance. A high-imped-
ance source can be accommodated either by
lengthening t
a 1µF capacitor between the positive and negative ana-
log inputs. The combination of the analog-input source
impedance and the capacitance at the analog input cre-
ates an RC filter that limits the analog input bandwidth.
The ADC’s input-tracking circuitry has a 1MHz small-
signal bandwidth, making it is possible to digitize high-
speed transient events and measure periodic signals
with bandwidths exceeding the ADC’s sampling rate by
using undersampling techniques. Anti-alias prefiltering
of the input signals is necessary to avoid high-frequen-
cy signals aliasing into the frequency band of interest.
Internal electrostatic-discharge (ESD) protection diodes
clamp all analog inputs to AV
the inputs to swing from (AGND - 0.3V) to (AV
0.3V) without damage. However, for accurate conver-
sions near full scale, the inputs must not exceed AV
by more than 50mV or be lower than AGND by 50mV. If
an analog input voltage exceeds the supplies, limit the
input current to 2mA.
The MAX1020/MAX1022/MAX1057/MAX1058 contain a
first-in/first-out (FIFO) buffer that holds up to 16 ADC
results plus one temperature result. The internal FIFO
allows the ADC to process and store multiple internally
clocked conversions and a temperature measurement
without being serviced by the serial bus.
If the FIFO is filled and further conversions are request-
ed without reading from the FIFO, the oldest ADC
results are overwritten by the new ADC results. Each
result contains 2 bytes, with the MSB preceded by four
leading zeros and the LSB followed by 2 sub-bits. After
each falling edge of CS, the oldest available pair of
bytes of data is available at DOUT, MSB first. When the
FIFO is empty, DOUT is zero.
ACQ
(only in clock mode 01) or by placing
Analog-Input Protection
DD
and AGND, allowing
Input Bandwidth
Internal FIFO
DD
DD
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