MAX11800ETC/V+T Maxim Integrated Products, MAX11800ETC/V+T Datasheet - Page 40

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MAX11800ETC/V+T

Manufacturer Part Number
MAX11800ETC/V+T
Description
IC TOUCH SCREEN CTRLR LP 12WQFN
Manufacturer
Maxim Integrated Products
Type
Resistiver
Datasheet

Specifications of MAX11800ETC/V+T

Touch Panel Interface
4-Wire
Number Of Inputs/keys
1 TSC
Resolution (bits)
12 b
Data Interface
Serial, SPI™
Data Rate/sampling Rate (sps, Bps)
105k
Voltage - Supply
1.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
12-WQFN Exposed Pad
Voltage Supply Source
Single Supply
Sampling Rate (per Second)
105k
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Low-Power, Ultra-Small Resistive Touch-Screen
Controllers with I
Figure 20. SPI Multiple-Byte Register Read Sequence—MAX11800/MAX11802
Figure 21. SPI Conversion Command—MAX11800/MAX11802
The sequence in Figures 20 and 21 shows the required
command format for issuing conversion requests. A
conversion request cannot be paired with multiple com-
mands or instructions. Any conversion command
issued while previous commands are being executed is
ignored.
The MAX11801/MAX11803 feature an I
compatible, 2-wire serial interface consisting of a serial-
data line (SDA) and a serial-clock line (SCL). SDA and
SCL
MAX11801/MAX11803 and the master at clock rates up
to 400kHz. Figure 22 shows the 2-wire interface timing
diagram. The master generates SCL and initiates data
transfer on the bus.
The master device writes data to the MAX11801/
MAX11803 by transmitting the proper slave address fol-
lowed by the register address and then the data word.
Each transmit sequence is framed by a START (S) or
repeated START (Sr) condition and a STOP (P) condi-
tion. Each word transmitted to the MAX11801/
MAX11803 is 8 bits long and is followed by an acknowl-
edge clock pulse.
A master reading data from the MAX11801/MAX11803
transmits the proper slave address followed by a series
SMBus is a trademark of Intel Corp.
40
SPI Conversion Command (MAX11800/MAX11802)
______________________________________________________________________________________
facilitate
DOUT
SCLK
DIN
CS
communication
1
I
2
(MAX11801/MAX11803)
C-Supported Sequence
A
i
[6:0]
SCLK
DIN
CS
7
8
between
9
A6
2
2
C/SMBus™-
1
C/SPI Interface
A5
2
D
i
[7:0]
A4
the
3
A3
4
16
A2
of nine SCL pulses. The MAX11801/MAX11803 trans-
mits data on SDA in sync with the master-generated
SCL pulses. The master acknowledges receipt of each
byte of data. Each read sequence is framed by a
START (S) or repeated START (Sr) condition, a not-
acknowledge, and a STOP (P) condition. SDA operates
as both an input and an open-drain output.
A pullup resistor, typically greater than 500Ω, is
required on SDA. SCL operates only as an input. A
pullup resistor, typically greater than 500Ω, is required
on SCL if there are multiple masters on the bus, or if the
single master has an open-drain SCL output. Series
resistors in line with SDA and SCL are optional. Series
resistors
MAX11801/MAX11803 from high-voltage spikes on the
bus lines and minimize crosstalk and undershoot of the
bus signals.
One data bit is transferred during each SCL cycle. The
data on SDA must remain stable during the high period
of the SCL pulse. Changes in SDA while SCL is high
are control signals (see the START and STOP
Conditions section).
SDA and SCL idle high when the bus is not in use. A
master initiates communication by issuing a START
condition. A START condition is a high-to-low transition
17
5
A1
6
D
i+1
A0
[7:0]
7
protect
W
8
24
START and STOP Conditions
25
the
D
i+2
digital
[7:0]
32
inputs
S
Bit Transfer
of
the

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