MAX11800ETC/V+T Maxim Integrated Products, MAX11800ETC/V+T Datasheet - Page 43

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MAX11800ETC/V+T

Manufacturer Part Number
MAX11800ETC/V+T
Description
IC TOUCH SCREEN CTRLR LP 12WQFN
Manufacturer
Maxim Integrated Products
Type
Resistiver
Datasheet

Specifications of MAX11800ETC/V+T

Touch Panel Interface
4-Wire
Number Of Inputs/keys
1 TSC
Resolution (bits)
12 b
Data Interface
Serial, SPI™
Data Rate/sampling Rate (sps, Bps)
105k
Voltage - Supply
1.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
12-WQFN Exposed Pad
Voltage Supply Source
Single Supply
Sampling Rate (per Second)
105k
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Send the slave address with the R/W bit set to 1 to initi-
ate a read operation. The MAX11801/MAX11803
acknowledge receipt of its slave address by pulling
SDA low during the 9th SCL clock pulse. Transmitted
data is valid on the rising edge of SCL. A STOP condi-
tion can be issued after any number of read data bytes.
The address pointer should be preset to a specific reg-
ister before a read command is issued. The master pre-
sets the address pointer by first sending the
MAX11801/MAX11803’s slave address with the R/W bit
set to 0 followed by the selected register address. A
repeated START condition is then sent followed by the
slave address with the R/W bit set to 1. The MAX11801/
MAX11803 then transmit the contents of the selected
Figure 27. Basic Single Read Sequence
Figure 28. I
Low-Power, Ultra-Small Resistive Touch-Screen
SDA
SCL
SDA
SCL
START
SDA (cont.)
START
DIRECTION
SCL (cont.)
SDA
SDA
SCL
2
1
C Multiple Read Sequence
BYTE 1: DEVICE ADDRESS
0
START
1
WRITE ADDRESS
0
BYTE 1: DEVICE ADDRESS
0
1
WRITE ADDRESS
0
0
______________________________________________________________________________________
A1 A0
1
Sr
1
0
W
INTO MAX11801/MAX11803
0
1
A1
A
N6
WRITE REGISTER START NUMBER
BYTE 2: FIRST REG NUMBER = N
A2
0
N5
0
W
N4
A = ACKNOWLEDGE
ACKNOWLEDGE GENERATED BY MAX11801/MAX11803
N3 N2 N1 N0 X
Read Data Format
1
A
0
N6 N5 N4 N3 N2 N1 N0
Controllers with I
WRITE REGISTER START NUMBER
BYTE 2: FIRST REG NUMBER = N
0
IN
1
A = ACKNOWLEDGE
A1
ACKNOWLEDGE GENERATED BY MAX11801/MAX11803
A
0
REPEATED
START
A0
A1
1
BYTE 3: DEVICE ADDRESS
W
0
A0
WRITE ADDRESS
X
0
ACK
OUT
1
A
R
0 A1 A0
REPEATED
START
~A = NOT ACKNOWLEDGE
N6
ACK
ACKNOWLEDGE GENERATED BY I
register. If the selected register supports autoincrement,
the register pointer automatically increments after trans-
mitting each data byte, making data in the next register
location available for access in the same transfer. Some
registers do not support autoincrement, usually
because they are at the end of a functional section or,
in the case of the FIFO, store multiple records.
The master acknowledges receipt of each data byte
received from the MAX11801/MAX11803 during the
“acknowledge clock period.” If the master requires
more data from the MAX11801/MAX11803, it brings the
acknowledge line low, indicating more data is expect-
ed. This sequence is repeated until the master termi-
nates with a not-acknowledge (~A) followed by a STOP
condition. Figure 27 illustrates the frame format for
R
A
N5
1
D7
D
BYTE 3: DEVICE ADDRESS
0
D
BYTE 4: REG(N)[7:0] DATA
N4
WRITE ADDRESS
0
D
D6
READ DATA
D
1
N3
D
2
C MASTER
D5
0
D
IN
A1
~A = NOT ACKNOWLEDGE
D
N2
OUT
D4
2
A2
D
ACKNOWLEDGE GENERATED BY I
A
C/SPI Interface
R
N1
D3
A
SEQUENTIAL READ
ADDITONAL
DATA BYTES
READ DATA
D
N0
D2
BYTE 4: REG(N)[7:0] DATA
D
D
X
D1
READ DATA
D
D
ACK
OUT
D
D
2
READ DATA (LAST BYTE)
C MASTER
D0
D
D
D
NACK
D
D
D
D
D
IN
STOP
~A
D
~A
STOP
STOP
43

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