ISL90842UIV1427Z-TK Intersil, ISL90842UIV1427Z-TK Datasheet - Page 9

• Manufacturer Part Number: ISL90842UIV1427Z-TK
• Description: IC POT DGTL QUAD 50K OHM 14TSSOP
• Manufacturer: Intersil
• Series: XDCP™r

Specifications of ISL90842UIV1427Z-TK

• Taps: 256
• Resistance (ohms): 50K
• Number Of Circuits: 4
• Temperature Coefficient: 45 ppm/°C Typical
• Memory Type: Volatile
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 14-TSSOP
• Resistance In Ohms: 50K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ISL90842UIV1427Z-TKTR

Write Operation
A Write operation requires a START condition, followed by a
valid Identification Byte, a valid Address Byte, a Data Byte,
and a STOP condition. After each of the three bytes, the
ISL90842 responds with an ACK. At this time, the device
enters its standby state (See Figure 11).
Read Operation
A Read operation consist of a three byte instruction followed
by one or more Data Bytes (See Figure 12). The master
initiates the operation issuing the following sequence: a
START, the Identification byte with the R/W bit set to “0”, an
Address Byte, a second START, and a second Identification
byte with the R/W bit set to “1”. After each of the three bytes,
the ISL90842 responds with an ACK. Then the ISL90842
transmits Data Bytes as long as the master responds with an
ACK during the SCL cycle following the eighth bit of each
byte. The master terminates the read operation (issuing a
STOP condition) following the last bit of the last Data Byte
(See Figure 12).
The Data Bytes are from the registers indicated by an
internal pointer. This pointer initial value is determined by the
Address Byte in the Read operation instruction, and
increments by one during transmission of each Data Byte.
After reaching the memory location 03h the pointer “rolls
over” to 00h, and the device continues to output data for
each ACK received.
SIGNAL AT SDA
FROM THE
SIGNALS
MASTER
SIGNALS FROM
THE SLAVE
S
T
A
R
T
0
IDENTIFICATION
1
BYTE WITH
0
R/W=0
1
0 A1A0
9
0
A
C
K
0 0 0
ADDRESS
BYTE
0
0 0
FIGURE 12. READ SEQUENCE
A
C
K
ISL90842
S
A
R
T
T
0
IDENTIFICATION
1
BYTE WITH
0
R/W=1
1 0 A1A0
1
A
C
K
FIRST READ
DATA BYTE
A
C
K
A
C
K
LAST READ
DATA BYTE
January 16, 2006
FN8096.1
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