MCP4351-103E/ST Microchip Technology, MCP4351-103E/ST Datasheet - Page 65

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MCP4351-103E/ST

Manufacturer Part Number
MCP4351-103E/ST
Description
IC DGTL POT QUAD 10K 20TSSOP
Manufacturer
Microchip Technology
Datasheet

Specifications of MCP4351-103E/ST

Taps
257
Resistance (ohms)
10K
Number Of Circuits
4
Temperature Coefficient
150 ppm/°C Typical
Memory Type
Volatile
Interface
SPI Serial
Voltage - Supply
1.8 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
20-TSSOP
Resistance In Ohms
10K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
8.4
In the design of a system with the MCP43XX devices,
the following considerations should be taken into
account:
8.4.1
The typical application will require a bypass capacitor
in order to filter high-frequency noise, which can be
induced onto the power supply’s traces. The bypass
capacitor helps to minimize the effect of these noise
sources on signal integrity.
appropriate bypass strategy.
In this example, the recommended bypass capacitor
value is 0.1 µF. This capacitor should be placed as
close (within 4 mm) to the device power pin (V
possible.
The power source supplying these devices should be
as clean as possible. If the application circuit has
separate digital and analog power supplies, V
V
FIGURE 8-6:
Connections.
 2010 Microchip Technology Inc.
SS
Power Supply Considerations
Layout Considerations
should reside on the analog plane.
W
A
B
Design Considerations
POWER SUPPLY
CONSIDERATIONS
0.1 µF
V
V
Typical Microcontroller
DD
SS
Figure 8-6
0.1 µF
U/D
CS
illustrates an
V
V
DD
SS
DD
DD
) as
and
8.4.2
Several layout considerations may be applicable to
your application. These may include:
8.4.2.1
Inductively-coupled AC transients and digital switching
noise can degrade the input and output signal integrity,
potentially masking the MCP43XX’s performance.
Careful board layout minimizes these effects and
increases the Signal-to-Noise Ratio (SNR). Multi-layer
boards utilizing a low-inductance ground plane,
isolated inputs, isolated outputs and proper decoupling
are critical to achieving the performance that the
silicon is capable of providing. Particularly harsh
environments may require shielding of critical signals.
If low noise is desired, breadboards and wire-wrapped
boards are not recommended.
8.4.2.2
The specification of the MCP43XX pinouts was done to
allow systems to be designed to easily support the use
of either the dual (MCP42XX) or quad (MCP43XX)
device.
Figure 8-7
quad device footprint. For the Rheostat devices, the
dual device is in the MSOP package, so the footprints
would need to be offset from each other.
FIGURE 8-7:
Package) vs. Dual Pinout.
Noise
Footprint Compatibility
PCB Area Requirements
P3W
SCK
P1W
P3W
SCK
P3A
P1B
P1A
P3B
P1B
P3B
SDI
V
SDI
V
CS
CS
SS
SS
Note 1: Pin 15 (RESET) is the Shutdown
MCP43X1 Quad Potentiometers
MCP43X2 Quad Rheostat
1
2
3
4
5
6
7
1
2
3
4
5
6
7
8
9
10
TSSOP
shows how the dual pinout devices fit on the
LAYOUT CONSIDERATIONS
TSSOP
Noise
Footprint Compatibility
(SHDN) pin on the MCP42x1 device.
MCP433X/435X
20
19
18
17
16
15
14
12
12
11
14
13
12
10
11
9
8
V
SDO
RESET
WP
P0B
P0W
P2A
P2W
P2B
P0A
P2W
P2B
V
SDO
P0B
P0W
P1W
Quad Pinout (TSSOP
DD
DD
MCP42X1 Pinout
MCP42X2 Pinout
DS22242A-page 65
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