CS4382A-CQZ Cirrus Logic Inc, CS4382A-CQZ Datasheet - Page 21

IC DAC 8CH 114DB 192KHZ 48LQFP

CS4382A-CQZ

Manufacturer Part Number
CS4382A-CQZ
Description
IC DAC 8CH 114DB 192KHZ 48LQFP
Manufacturer
Cirrus Logic Inc
Datasheets

Specifications of CS4382A-CQZ

Package / Case
48-LQFP
Number Of Bits
24
Data Interface
Serial
Number Of Converters
8
Voltage Supply Source
Analog and Digital
Power Dissipation (max)
680mW
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Conversion Rate
192 KSPS
Resolution
24 bit
Interface Type
Serial
Operating Supply Voltage
5 V
Operating Temperature Range
+ 85 C
Maximum Power Dissipation
390 mW
Mounting Style
SMD/SMT
Number Of Dac Outputs
8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1524 - BOARD EVAL FOR CS4382A DAC
Settling Time
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
598-1061

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CS4382A-CQZ
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
Part Number:
CS4382A-CQZR
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
DS618F2
4. APPLICATIONS
The CS4382A serially accepts two’s-complement formatted PCM data at standard audio sample rates including 48,
44.1, and 32 kHz in SSM, 96, 88.2, and 64 kHz in DSM, and 192, 176.4, and 128 kHz in QSM. Audio data is input
via the serial data input pins (SDINx). The Left/Right Clock (LRCK) determines which channel is currently being input
on SDINx, and the Serial Clock (SCLK) clocks audio data into the input data buffer.
The CS4382A can be configured in Hardware Mode by the M0, M1, M2, M3, and DSD_EN pins and in Software
Mode through I²C or SPI.
4.1
4.2
(sample-rate range)
Note:
(100 to 200 kHz)
(50 to 100 kHz)
Double-Speed
Single-Speed
Speed Mode
(4 to 50 kHz)
Quad-Speed
Master Clock
MCLK/LRCK must be an integer ratio as shown in
cy at which words for each channel are input to the device. The MCLK-to-LRCK frequency ratio is detected
automatically during the initialization sequence by counting the number of MCLK transitions during a single
LRCK period. Internal dividers are then set to generate the proper internal clocks.
standard audio sample rates and the required MCLK and LRCK frequencies. Please note there is no re-
quired phase relationship, but MCLK, LRCK, and SCLK must be synchronous.
Mode Select
In Hardware Mode, operation is determined by the Mode Select pins. The states of these pins are continu-
ally scanned for any changes; however, the mode should only be changed while the device is in reset
(RST pin low) to ensure proper switching from one mode to another. These pins require connection to sup-
ply or ground as outlined in
Tables 2
In Software Mode, the operational mode and data format are set in the FM and DIF registers. See
Interface Format (DIF)” on page 34
These modes are only available in Software Mode by setting the MCLKDIV bit = 1.
MCLK Ratio
MCLK Ratio
MCLK Ratio
-
4
show the decode of these pins.
Sample
(kHz)
176.4
Rate
44.1
88.2
192
32
48
64
96
Figure
Table 1. Common Clock Frequencies
11.2896
12.2880
11.2896
12.2880
11.2896
12.2880
8.1920
8.1920
256x
128x
64x
and
6. VLC supplies M0, M1, and M2. VLS supplies M3 and DSD_EN.
“Functional Mode (FM)” on page
12.2880
16.9344
18.4320
12.2880
16.9344
18.4320
16.9344
18.4320
384x
192x
96x
Table
MCLK (MHz)
1. The LRCK frequency is equal to Fs, the frequen-
16.3840
22.5792
24.5760
16.3840
22.5792
24.5760
22.5792
24.5760
512x
256x
128x
40.
24.5760
33.8688
36.8640
24.5760
33.8688
36.8640
33.8688
36.8640
768x
384x
192x
Table 1
illustrates several
Mode Only
Software
49.1520
49.1520
49.1520
32.7680
45.1584
32.7680
45.1584
45.1584
1024x*
CS4382A
512x*
256x*
“Digital
21

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