AD5327BRUZ Analog Devices Inc, AD5327BRUZ Datasheet - Page 17

• Manufacturer Part Number: AD5327BRUZ
• Description: IC DAC 12BIT QUAD 2.5V 16-TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD5327BRUZ

• Data Interface: Serial
• Settling Time: 8µs
• Number Of Bits: 12
• Number Of Converters: 4
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 4.5mW
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Resolution (bits): 12bit
• Sampling Rate: 125kSPS
• Input Channel Type: Serial
• Supply Voltage Range - Analog: 2.5V To 5.5V
• Supply Current: 500µA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SERIAL INTERFACE
The AD5307/AD5317/AD5327 are controlled over versatile 3-wire
serial interfaces that operate at clock rates of up to 30 MHz and
are compatible with SPI, QSPI, MICROWIRE, and DSP
interface standards.
INPUT SHIFT REGISTER
The input shift register is 16 bits wide. Data is loaded into the
device as a 16-bit word under the control of a serial clock input,
SCLK. The timing diagram for this operation is shown in
Figure 3. The 16-bit word consists of four control bits followed
by 8, 10, or 12 bits of DAC data, depending on the device type.
Data is loaded MSB first (Bit 15), and the first two bits
determine whether the data is for DAC A, DAC B, DAC C, or
DAC D. Bit 13 and Bit 12 control the operating mode of the
DAC. Bit 13 is GAIN, which determines the output range of the
part. Bit 12 is BUF, which controls whether the reference inputs
are buffered or unbuffered.
Table 6. Address Bits for the AD53x7
A1 (Bit 15)
0
0
1
1
CONTROL BITS
GAIN controls the output range of the addressed DAC.
BUF controls whether reference of the addressed DAC is
buffered or unbuffered.
0: output range of 0 V to V
1: output range of 0 V to 2 V
0: unbuffered reference.
1: buffered reference.
A0 (Bit 14)
0
1
0
1
REF
REF
.
BIT 15
(MSB)
BIT 15
(MSB)
BIT 15
(MSB)
A1
A1
.
A1
A0
A0
A0
DAC Addressed
DAC A
DAC B
DAC C
DAC D
GAIN
GAIN
GAIN
BUF
BUF D11 D10
BUF
Figure 33. AD5307 Input Shift Register Contents
Figure 34. AD5317 Input Shift Register Contents
Figure 35. AD5327 Input Shift Register Contents
D9
D7
D8
D6
D7
D9
Rev. C | Page 17 of 28
D5
DATA BITS
D6
D8
D4
DATA BITS
D5
D7
D3
DATA BITS
D4
D6
The AD5327 uses all 12 bits of DAC data; the AD5317 uses
10 bits and ignores the 2 LSBs. The AD5307 uses eight bits and
ignores the last four bits. The data format is straight binary, with
all 0s corresponding to 0 V output and all 1s corresponding to
full-scale output (V
The SYNC input is a level-triggered input that acts as a frame
synchronization signal and chip enable. Data can be transferred
into the device only while SYNC is low. To start the serial data
transfer, SYNC should be taken low, observing the minimum
SYNC to SCLK falling edge set-up time, t
low, serial data is shifted into the device’s input shift register on
the falling edges of SCLK for 16 clock pulses. In standalone
mode (DCEN = 0), any data and clock pulses after the 16th
falling edge of SCLK are ignored, and no further serial data
transfer can occur until SYNC is taken high and low again.
SYNC can be taken high after the falling edge of the 16th SCLK
pulse, observing the minimum SCLK falling edge to SYNC
rising edge time, t
After the end of serial data transfer, data is automatically trans-
ferred from the input shift register to the input register of the
selected DAC. If SYNC is taken high before the 16th falling
edge of SCLK, the data transfer is aborted and the DAC input
registers are not updated.
When data has been transferred into the input register of a DAC,
the corresponding DAC register and DAC output can be updated
by taking LDAC low. CLR is an active low, asynchronous clear
that clears the input registers and DAC registers to all 0s.
D2
D3
D5
D1
D2
D4
D0
D1
D3
X
D0
D2
7
X
.
REF
D1
X
− 1 LSB).
X
AD5307/AD5317/AD5327
BIT 0
(LSB)
BIT 0
(LSB)
BIT 0
(LSB)
D0
X
X
4
. After SYNC goes