AD5327BRUZ Analog Devices Inc, AD5327BRUZ Datasheet - Page 8

• Manufacturer Part Number: AD5327BRUZ
• Description: IC DAC 12BIT QUAD 2.5V 16-TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD5327BRUZ

• Data Interface: Serial
• Settling Time: 8µs
• Number Of Bits: 12
• Number Of Converters: 4
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 4.5mW
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Resolution (bits): 12bit
• Sampling Rate: 125kSPS
• Input Channel Type: Serial
• Supply Voltage Range - Analog: 2.5V To 5.5V
• Supply Current: 500µA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD5307/AD5317/AD5327
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 5. Pin Function Descriptions
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Mnemonic
CLR
LDAC
V
V
V
V
V
V
DCEN
PD
V
GND
DIN
SCLK
SYNC
SDO
DD
OUT
OUT
OUT
REF
REF
OUT
AB
CD
A
B
C
D
Description
Active Low Control Input. Loads all 0s to all input and DAC registers. Therefore, the outputs also go to 0 V.
Active Low Control Input. Transfers the contents of the input registers to their respective DAC registers. Pulsing this
pin low allows any or all DAC registers to be updated if the input registers have new data. This allows simultaneous
update of all DAC outputs. Alternatively, this pin can be tied permanently low.
Power Supply Input. These parts can be operated from 2.5 V to 5.5 V, and the supply should be decoupled with a 10 μF
capacitor in parallel with a 0.1 μF capacitor to GND.
Buffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
Buffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
Buffered Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.
Reference Input Pin for DAC A and DAC B. It can be configured as a buffered or unbuffered input to each or both of
the DACs, depending on the state of the BUF bits in the serial input words to DAC A and DAC B. It has an input range
of 0.25 V to V
Reference Input Pin for DAC C and DAC D. It can be configured as a buffered or unbuffered input to each or both of
the DACs, depending on the state of the BUF bits in the serial input words to DAC C and DAC D. It has an input range
of 0.25 V to V
Enables the Daisy-Chaining Option. It should be tied high if the part is being used in a daisy chain, and tied low if it is
being used in standalone mode.
Active Low Control Input. It acts like a hardware power-down option. All DACs go into power-down mode when this
pin is tied low. The DAC outputs go into a high impedance state, and the current consumption of the part drops to
300 nA @ 5 V (90 nA @ 3 V).
Buffered Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.
Ground Reference Point for All Circuitry on the Part.
Serial Data Input. These devices each have a 16-bit shift register. Data is clocked into the register on the falling edge of
the serial clock input. The DIN input buffer is powered down after each write cycle.
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be
transferred at rates of up to 30 MHz. The SCLK input buffer is powered down after each write cycle.
Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it powers
on the SCLK and DIN buffers and enables the input shift register. Data is transferred in on the falling edges of the
following 16 clocks. If SYNC is taken high before the 16th falling edge, the rising edge of SYNC acts as an interrupt and
the write sequence is ignored by the device.
Serial Data Output. Can be used for daisy-chaining a number of these devices together or for reading back the data in
the shift register for diagnostic purposes. The serial data is transferred on the rising edge of SCLK and is valid on the
falling edge of the clock.
DD
DD
in unbuffered mode and 1 V to V
in unbuffered mode and 1 V to V
V
V
V
V
V
REF
REF
LDAC
OUT
OUT
OUT
V
CLR
DD
AB
CD
Figure 5. Pin Configuration
A
B
C
Rev. C | Page 8 of 28
1
2
3
4
5
6
7
8
(Not to Scale)
AD5307/
AD5317/
AD5327
TOP VIEW
DD
DD
in buffered mode.
in buffered mode.
16
15
14
13
12
11
10
9
SDO
SYNC
SCLK
DIN
GND
V
PD
DCEN
OUT
D