ADV7123JSTZ330 Analog Devices Inc, ADV7123JSTZ330 Datasheet - Page 10

• Manufacturer Part Number: ADV7123JSTZ330
• Description: IC DAC VIDEO 3CH 330MHZ 48-LQFP
• Manufacturer: Analog Devices Inc

Specifications of ADV7123JSTZ330

• Data Interface: Parallel
• Settling Time: 15ns
• Number Of Bits: 10
• Number Of Converters: 3
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 30mW
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Resolution (bits): 10bit
• Sampling Rate: 330MSPS
• Input Channel Type: Parallel
• Supply Current: 16mA
• Digital Ic Case Style: QFP
• No. Of Pins: 48
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADV7123
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 8. Pin Function Descriptions
Pin No.
1 to 10,
14 to 23,
39 to 48
11
12
13, 29, 30
24
25, 26
27, 31, 33
28, 32, 34
35
36
Mnemonic
G0 to G9,
B0 to B9,
R0 to R9
BLANK
SYNC
V
CLOCK
GND
IOB, IOG, IOR
IOB, IOG, IOR
COMP
V
AA
REF
Ground. All GND pins must be connected.
Description
Red, Green, and Blue Pixel Data Inputs (TTL Compatible). Pixel data is latched on the rising edge of CLOCK. R0,
G0, and B0 are the least significant data bits. Unused pixel data inputs should be connected to either the
regular printed circuit board (PCB) power or ground plane.
Composite Blank Control Input (TTL Compatible). A Logic 0 on this control input drives the analog outputs,
IOR, IOB, and IOG, to the blanking level. The BLANK signal is latched on the rising edge of CLOCK. While
BLANK is a Logic 0, the R0 to R9, G0 to G9, and B0 to B9 pixel inputs are ignored.
Composite Sync Control Input (TTL Compatible). A Logic 0 on the SYNC input switches off a 40 IRE current
source. This is internally connected to the IOG analog output. SYNC does not override any other control or
data input; therefore, it should only be asserted during the blanking interval. SYNC is latched on the rising
edge of CLOCK. If sync information is not required on the green channel, the SYNC input should be tied to
Logic 0.
Analog Power Supply (5 V ± 5%). All V
Clock Input (TTL Compatible). The rising edge of CLOCK latches the R0 to R9, G0 to G9, B0 to B9, SYNC, and
BLANK pixel and control inputs. It is typically the pixel clock rate of the video system. CLOCK should be driven
by a dedicated TTL buffer.
Differential Red, Green, and Blue Current Outputs (High Impedance Current Sources). These RGB video
outputs are specified to directly drive RS-343A and RS-170 video levels into a doubly terminated 75 Ω load. If
the complementary outputs are not required, these outputs should be tied to ground.
Red, Green, and Blue Current Outputs. These high impedance current sources are capable of directly driving a
doubly terminated 75 Ω coaxial cable. All three current outputs should have similar output loads whether or
not they are all being used.
Compensation Pin. This is a compensation pin for the internal reference amplifier. A 0.1 μF ceramic capacitor
must be connected between COMP and V
Voltage Reference Input for DACs or Voltage Reference Output (1.235 V).
BLANK
SYNC
G0
G1
G2
G3
G4
G5
G6
G7
G8
G9
10
12
11
1
2
3
4
5
6
7
8
9
48 47 46 45 44 43 42 41 40 39 38 37
13 14 15 16 17 18 19 20 21 22 23 24
PIN 1
INDICATOR
Figure 3. Pin Configuration
Rev. D | Page 10 of 24
(Not to Scale)
ADV7123
TOP VIEW
AA
pins on the ADV7123 must be connected.
AA
.
36
35
34
33
32
29
28
27
31
30
26
25
V
COMP
IOR
IOR
IOG
IOG
V
V
IOB
IOB
GND
GND
REF
AA
AA