CS4334-DSZ Cirrus Logic Inc, CS4334-DSZ Datasheet - Page 12

• Manufacturer Part Number: CS4334-DSZ
• Description: IC DAC STER 24BIT 96KHZ 8-SOIC
• Manufacturer: Cirrus Logic Inc

Specifications of CS4334-DSZ

• Data Interface: Serial
• Number Of Bits: 24
• Number Of Converters: 2
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 104mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC
• Resolution (bits): 24bit
• Sampling Rate: 96kSPS
• Input Channel Type: Serial
• Supply Voltage Range - Analog: 4.75V To 5.5V
• Supply Current: 15mA
• Digital Ic Case Style: SOIC
• Package: 8SOIC
• Resolution: 24 Bit
• Conversion Rate: 96 KSPS
• Architecture: Delta-Sigma
• Digital Interface Type: Serial
• Number Of Outputs Per Chip: 2
• Output Type: Voltage
• Full Scale Error: ±5(Typ) %FSR
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1510 - BOARD EVAL FOR CS4334 CODEC
• Settling Time: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 598-1631

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3. GENERAL DESCRIPTION
The CS4334 family of devices offers a complete stereo digital-to-analog system including digital interpolation,
fourth-order delta-sigma digital-to-analog conversion, digital de-emphasis and analog filtering, as shown in
Figure
The primary purpose of using delta-sigma modulation techniques is to avoid the limitations of resistive laser trimmed
digital-to-analog converter architectures by using an inherently linear 1-bit digital-to-analog converter. The advan-
tages of a 1-bit digital-to-analog converter include: ideal differential linearity, no distortion mechanisms due to resis-
tor matching errors and no linearity drift over time and temperature due to variations in resistor values.
The CS4334 family of devices supports two modes of operation. The devices operate in Base Rate Mode (BRM)
when MCLK/LRCK is 256, 384 or 512 and in High Rate Mode (HRM) when MCLK/LRCK is 128 or 192. High Rate
Mode allows input sample rates up to 100 kHz.
3.1
3.2
3.3
3.4
Digital
Input
8. This architecture provides a high tolerance to clock jitter.
Digital Interpolation Filter
The digital interpolation filter increases the sample rate, Fs, by a factor of 4 and is followed by a 32× digital
sample-and-hold (16× in HRM). This filter eliminates images of the baseband audio signal which exist at
multiples of the input sample rate. The resulting frequency spectrum has images of the input signal at mul-
tiples of 4 Fs. These images are easily removed by the on-chip analog low-pass filter and a simple external
analog filter (see
Delta-Sigma Modulator
The interpolation filter is followed by a fourth order delta-sigma modulator which converts the interpolation
filter output into 1-bit data at a rate of 128 Fs in BRM (or 64 Fs in HRM).
Switched-Capacitor DAC
The delta-sigma modulator is followed by a digital-to-analog converter which translates the 1-bit data into a
series of charge packets. The magnitude of the charge in each packet is determined by sampling of a volt-
age reference onto a switched capacitor, where the polarity of each packet is controlled by the 1-bit data.
This technique greatly reduces the sensitivity to clock jitter and provides low-pass filtering of the output.
Analog Low-Pass Filter
The final signal stage consists of a continuous-time low-pass filter which serves to smooth the output and
attenuate out-of-band noise.
Interpolator
Figure
1).
Figure 8. System Block Diagram
Delta-Sigma
Modulator
Confidential Draft
3/11/08
DAC
Low-Pass
Analog
Filter
CS4334/5/8/9
Analog
Output
DS248F5