MT48LC8M32B2P-6 Micron Technology Inc, MT48LC8M32B2P-6 Datasheet
MT48LC8M32B2P-6
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MT48LC8M32B2P-6 Summary of contents
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... Marking 8M32B2 NOTE: None The # symbol indicates signal is active LOW Configuration Refresh Count Row Addressing SETUP HOLD Bank Addressing TIME TIME Column Addressing 1.5ns 1ns 2ns 1ns 1 256Mb: x32 SDRAM 86-Pin TSOP DQ0 2 85 DQ15 DQ1 4 83 DQ14 DQ2 5 82 DQ13 V ...
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... BURST READ/SINGLE WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 CONCURRENT AUTO PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 READ with AUTO PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 WRITE with AUTO PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 09005aef8140ad6d MT48LC8M32B2TOC.fm - Rev. B 10/04 EN Micron Technology, Inc., reserves the right to change products or specifications without notice. 2 ©2003 Micron Technology, Inc. All rights reserved. 256Mb: x32 SDRAM ...
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... List of Figures Figure 1: Pin Assignment (Top View) 86-Pin TSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Figure 2: 90-Ball FBGA Assignment (Top View Figure 3: Functional Block Diagram – 8 Meg x 32 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Figure 4: Mode Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Figure 5: CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Figure 6: Activating a Specific Row in a Specific Bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 t Figure 7: Example: Meeting Figure 8: READ Command ...
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... Electrical Characteristics and Recommended AC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . .34 Table 13: AC Functional Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Table 14: I Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 DD 09005aef8140ad6d MT48LC8M32B2LOT.fm - Rev. B 10/04 EN Micron Technology, Inc., reserves the right to change products or specifications without notice. 4 ©2003 Micron Technology, Inc. All rights reserved. 256Mb: x32 SDRAM ...
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... DQ22 DQ20 DQ17 DQ18 DQ16 DQM2 V DD A10 BA1 A11 BA0 CS# RAS# CAS# WE# DQM0 V DQ7 DQ6 DQ5 DQ1 DQ3 DQ4 DQ0 DQ2 DD Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. SDRAM ...
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... SDRAM Part Number PART NUMBER ARCHITECTURE MT48LC8M32B2TG 8 Meg x 32 MT48LC8M32B2P 8 Meg x 32 MT48LC8M32B2F5 8 Meg x 32 MT48LC8M32B2B5 8 Meg x 32 General Description The 256Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing 268,435,456-bits internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK) ...
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... Figure 3: Functional Block Diagram – 8 Meg x 32 SDRAM CKE CLK CONTROL CS# LOGIC WE# CAS# RAS# REFRESH COUNTER MODE REGISTER 12 12 A0–A11, ADDRESS 14 BA0, BA1 REGISTER 09005aef8140ad6d MT48LC8M32B2_2.fm - Rev. B 10/04 EN BANK 0 12 BANK 0 ROW- 12 ROW- ADDRESS MUX ADDRESS MEMORY 4,096 LATCH & (4,096 x 256 x 32) ...
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... MT48LC8M32B2_2.fm - Rev. B 10/04 EN TYPE Input Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of CLK. CLK also increments the internal burst counter and controls the output registers. Input Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal. ...
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... MT48LC8M32B2_2.fm - Rev. B 10/04 EN TYPE Input Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of CLK. CLK also increments the internal burst counter and controls the output registers. Input Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal. ...
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... Functional Description In general, this 256Mb SDRAM (2 Meg banks quad-bank DRAM that operates at 3.3V and includes a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the 67,108,864-bit banks is organized as 4,096 rows by 512 columns by 32-bits. Read and write accesses to the SDRAM are burst ori- ented ...
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... A0–A8 Cn (Location Cn + 4... 0–511) ...Cn-1, Cn... Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. SDRAM TYPE = INTERLEAVED 0-1 1-0 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 Not Supported ...
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... CLK COMMAND READ NOP Table 5: CAS Latency ALLOWABLE OPERATING SPEED ≤50 -6 ≤50 -7 Micron Technology, Inc., reserves the right to change products or specifications without notice. 12 256Mb: x32 SDRAM NOP OUT NOP NOP OUT t AC DON’T CARE UNDEFINED FREQUENCY (MHZ ≤100 ≤166 ≤100 ≤ ...
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... Operations already in progress are not affected. NO OPERATION (NOP) The NO OPERATION (NOP) command is used to per- form a NOP to an SDRAM which is selected (CS# is LOW). This prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected. ...
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... RFC), once every 64ms. SELF REFRESH The SELF REFRESH command can be used to retain data in the SDRAM, even if the rest of the system is powered down. When in the self refresh mode, the SDRAM retains data without external clocking. The SELF REFRESH command is initiated like an AUTO REFRESH command except CKE is disabled (LOW) ...
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... Operations Bank/Row Activation Before any READ or WRITE commands can be issued to a bank within the SDRAM, a row in that bank must be “opened.” This is accomplished via the ACTIVE command, which selects both the bank and the row to be activated. See Figure 6. ...
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... This is shown in Figure 10 for CAS latencies of one, two and three; data element either the last of a burst of four or the last desired of a longer burst. SDRAMs use a pipelined architecture and there- fore does not require the 2n rule associated with a prefetch architecture. A READ command can be initi- ated on any clock cycle following a previous READ command ...
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... T5 NOP D OUT OUT NOP NOP D D OUT OUT OUT NOP NOP NOP cycles OUT OUT OUT OUT DON’T CARE Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. SDRAM ...
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... I/O contention can be avoided given system design, there may be a possibility that the device driving the input data will go Low-Z before the SDRAM DQs go High-Z. In this case, at least a single- cycle delay should occur between the last read data and the WRITE command. ...
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... PRECHARGE command is that it requires that the command and address buses be available at the appropriate time to issue the command; the advantage of the PRECHARGE command is that it can be used to truncate fixed-length or full-page bursts. Micron Technology, Inc., reserves the right to change products or specifications without notice. 19 256Mb: x32 SDRAM Clock Cycle READ ...
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... Micron Technology, Inc., reserves the right to change products or specifications without notice. 20 256Mb: x32 NOP NOP ACTIVE BANK a, ROW NOP NOP ACTIVE BANK a, ROW D OUT NOP NOP ACTIVE cycles BANK a, ROW D D OUT OUT DON’T CARE ©2003 Micron Technology, Inc. All rights reserved. SDRAM ...
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... WRITE command, and data Micron Technology, Inc., reserves the right to change products or specifications without notice. 21 256Mb: x32 T5 T6 NOP NOP T5 T6 NOP NOP D OUT NOP NOP NOP cycles D D OUT OUT DON’T CARE ©2003 Micron Technology, Inc. All rights reserved. SDRAM ...
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... WRITE command, and the data provided coincident with the new command applies to the new command. An example is shown in Figure 18. Data either the last of a burst of two or the last desired of a longer burst. This 256Mb SDRAM uses a pipelined Figure 17: WRITE Burst T0 T1 ...
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... NOTE: The WRITE command may be to any bank, and the READ command may be to any bank. DQM is LOW for illustration. Micron Technology, Inc., reserves the right to change products or specifications without notice. 23 256Mb: x32 SDRAM WRITE WRITE WRITE WRITE BANK, BANK, BANK, ...
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... CKE HIGH CS# RAS# CAS# WE# A0-A9, A11 All Banks A10 Bank Selected BANK BA0, BA1 ADDRESS VALID ADDRESS t CKS). Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. SDRAM t RP) DON’T CARE ...
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... access command to (READ or WRITE) another bank while an access command with auto precharge enabled is executing is not allowed by SDRAMs, unless the SDRAM supports CONCURRENT AUTO PRE- CHARGE. Micron SDRAMs support CONCURRENT AUTO PRECHARGE. Four cases where CONCURRENT AUTO PRECHARGE occurs are defined below. ...
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... Interrupt Burst, Precharge Idle BANK BANK n WRITE with Burst of 4 Write-Back BANK m, COL DON’T CARE - met, where WR begins when the Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. SDRAM ...
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... WRITE - AP NOP NOP NOP BANK m Interrupt Burst, Write-Back Precharge BANK BANK BANK m WRITE with Burst of 4 Write-Back BANK m, COL DON’T CARE Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. SDRAM ...
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... H NOTE: 1. CKE is the logic state of CKE at clock edge n; CKE n 2. Current state is the state of the SDRAM immediately prior to clock edge n. 3. COMMAND is the command registered at clock edge n, and ACTION n 4. All states and sequences not shown are illegal or reserved. 5. Exiting power-down at clock edge n will put the device in the all banks idle state in time for clock edge (provided ...
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... RP is met, the bank will be in the idle state. 29 256Mb: x32 COMMAND (ACTION) t XSR has been met (if the previous t RCD has been met. No data bursts met. t RCD is met. Once Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. SDRAM NOTES ...
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... Does not affect the state of the bank and acts as a NOP to that bank. 09005aef8140ad6d MT48LC8M32B2_2.fm - Rev. B 10/ met, the SDRAM will be in the all banks idle state. t MRD is met, the SDRAM will be in the all banks idle state met, all banks will be in the idle state. ...
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... RP is met, the bank will be in the idle state. 31 256Mb: x32 COMMAND (ACTION) t XSR has been met (if the previous t RCD has been met. No data bursts/ Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. SDRAM NOTES ...
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... WRITE to bank m (Figure 30). 09005aef8140ad6d MT48LC8M32B2_2.fm - Rev. B 10/ begins when the READ to bank m is registered. The last valid WRITE to Micron Technology, Inc., reserves the right to change products or specifications without notice. 32 256Mb: x32 SDRAM met, where WR ©2003 Micron Technology, Inc. All rights reserved. ...
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... SYMBOL MIN ≤ OUT SYMBOL Micron Technology, Inc., reserves the right to change products or specifications without notice. 33 256Mb: x32 SDRAM Q Supply . . . . . . . . . . . . . 0°C to +70°C A (IT -40°C to +85°C A MAX UNITS NOTES -0.3 0 µ µA 2.4 – V – 0.4 V MIN MAX UNITS 2 ...
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... CMH t 1.5 CMS 1.5 DS CL=3 t 5 7 120K t RAS RFC t 18 RCD t REF RRD 0.3 1 CLK+ WR 6ns 12ns 70 t XSR Micron Technology, Inc., reserves the right to change products or specifications without notice. 34 256Mb: x32 SDRAM -7 MIN MAX UNITS 2. 120K ...
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... DQD t 0 DQM t 2 DQZ t 0 DWD DAL ( DAL ( DAL ( DPL 1 t BDL t 1 CDL t 2 RDL t 2 MRD ROH ( ROH ( ROH (1) Micron Technology, Inc., reserves the right to change products or specifications without notice. 35 256Mb: x32 SDRAM -7 UNITS NOTES ...
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... RFC (MIN) 36 256Mb: x32 MAX SYMBOL -6 -7 UNITS I 1 210 190 1.2 1 165 145 335 295 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. SDRAM NOTES 3, 18, 19 12, 19 18, 19 12, 18, 19 ...
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... CL is reduced 143 MHz for -7; 166 MHz for -6. overshoot: V (MAX (MIN) = -1.2V for a pulse width ≤ 3ns and PRECHARGE commands). CKE may 10ns 10ns and higher) in man- ©2003 Micron Technology, Inc. All rights reserved. SDRAM t RP; clock( 1.2V for a under for 100 ...
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... RP t RFC AUTO REFRESH AUTO REFRESH Micron Technology, Inc., reserves the right to change products or specifications without notice. 38 256Mb: x32 SDRAM LOAD MODE NOP NOP NOP ( ( REGISTER ) ) ( ( ) ) ( ...
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... Input buffers gated off while in power-down mode Exit power-down mode Micron Technology, Inc., reserves the right to change products or specifications without notice. 39 256Mb: x32 SDRAM CKS NOP ACTIVE ROW ROW BANK All banks idle DON’T CARE UNDEFINED ©2003 Micron Technology, Inc. All rights reserved. ...
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... Figure 33: Clock Suspend Mode NOP NOP NOP OUT OUT t LZ Micron Technology, Inc., reserves the right to change products or specifications without notice. 40 256Mb: x32 NOP WRITE 2 COLUMN e BANK OUT ©2003 Micron Technology, Inc. All rights reserved. SDRAM T9 NOP OUT DON’T CARE UNDEFINED ...
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... RP t RFC Micron Technology, Inc., reserves the right to change products or specifications without notice. 41 256Mb: x32 SDRAM AUTO NOP NOP ACTIVE ( ( REFRESH ) ) ( ( ) ) ( ( ) ) ( ( ...
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... RP Enter self refresh mode Exit self refresh mode (Restart refresh time base) CLK stable prior to exiting self refresh mode Micron Technology, Inc., reserves the right to change products or specifications without notice. 42 256Mb: x32 SDRAM CKS ...
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... DISABLE AUTO PRECHARGE BANK BANK RCD CAS Latency t RAS t RC Micron Technology, Inc., reserves the right to change products or specifications without notice. 43 256Mb: x32 T4 T5 NOP ACTIVE ROW ROW BANK OUT DON’T CARE UNDEFINED ©2003 Micron Technology, Inc. All rights reserved. SDRAM ...
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... CAS Latency 44 256Mb: x32 NOP PRECHARGE NOP ALL BANKS SINGLE BANK BANK OUT OUT OUT Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. SDRAM T8 ACTIVE ROW ROW BANK DON’T CARE UNDEFINED ...
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... COLUMN m 2 BANK OUT t LZ CAS Latency 45 256Mb: x32 NOP NOP NOP OUT OUT OUT Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. SDRAM T8 ACTIVE ROW ROW BANK DON’T CARE UNDEFINED ...
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... NOP ACTIVE t CMS t CMH COLUMN m 2 ROW ROW BANK 0 BANK OUT t LZ CAS Latency - BANK 0 t RCD - BANK 4 Micron Technology, Inc., reserves the right to change products or specifications without notice. 46 256Mb: x32 SDRAM NOP READ NOP COLUMN b 2 ENABLE AUTO PRECHARGE BANK ...
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... m OUT OUT OUT ( ( ) ) Full page completed 3 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. SDRAM NOP NOP m+1 OUT t HZ DON’T CARE UNDEFINED ...
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... READ NOP NOP t CMS t CMH COLUMN m 2 BANK OUT CAS Latency Micron Technology, Inc., reserves the right to change products or specifications without notice. 48 256Mb: x32 SDRAM NOP NOP NOP NOP OUT OUT ©2003 Micron Technology, Inc. All rights reserved. DON’T CARE ...
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... COLUMN m 3 DISABLE AUTO PRECHARGE BANK Micron Technology, Inc., reserves the right to change products or specifications without notice. 49 256Mb: x32 PRECHARGE NOP ACTIVE ROW ALL BANKS ROW SINGLE BANK BANK BANK t RP DON’T CARE ©2003 Micron Technology, Inc. All rights reserved. SDRAM ...
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... COLUMN m 3 BANK > CK). Micron Technology, Inc., reserves the right to change products or specifications without notice. 50 256Mb: x32 NOP PRECHARGE NOP ALL BANKs SINGLE BANK BANK ©2003 Micron Technology, Inc. All rights reserved. SDRAM T8 ACTIVE ROW ROW BANK DON’T CARE UNDEFINED ...
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... MT48LC8M32B2_2.fm - Rev. B 10/ WRITE NOP NOP NOP t CMH BANK > CK). 51 256Mb: x32 NOP NOP NOP Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. SDRAM T9 ACTIVE ROW ROW BANK DON’T CARE UNDEFINED ...
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... T7 T8 WRITE NOP NOP COLUMN b 3 ENABLE AUTO PRECHARGE BANK BANK BANK 0 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. SDRAM T9 ACTIVE ROW ROW BANK RCD - BANK BANK 4 DON’T CARE ...
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... Full-page burst does not self-terminate. Can use BURST TERMINATE command to stop. Full page completed Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. SDRAM NOP 2, 3 DON’T CARE ...
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... WRITE NOP NOP t CMS t CMH COLUMN m 2 ENABLE AUTO PRECHARGE DISABLE AUTO PRECHARGE BANK Micron Technology, Inc., reserves the right to change products or specifications without notice. 54 256Mb: x32 SDRAM NOP NOP NOP DON’T CARE ©2003 Micron Technology, Inc. All rights reserved. ...
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... MAX 55 256Mb: x32 SEE DETAIL A +0.03 0.15 -0.02 +0.10 0.10 -0.05 0.50 ±0.10 DETAIL A Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. SDRAM 0.25 GAGE PLANE 0.80 TYP ...
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... Sn, 3%Ag, 0.5% Cu (B5) SOLDER MASK DEFINED BALL PADS: Ø0.40 SUBSTRATE MATERIAL: PLASTIC LAMINATE MOLD COMPOUND: EPOXY NOVOLAC BALL A1 ID 1.00 MAX Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. SDRAM ...