MT45W2MW16PAFA85WT Micron Technology Inc, MT45W2MW16PAFA85WT Datasheet - Page 26
MT45W2MW16PAFA85WT
Manufacturer Part Number
MT45W2MW16PAFA85WT
Description
Manufacturer
Micron Technology Inc
Datasheet
1.MT45W2MW16PAFA85WT.pdf
(27 pages)
Specifications of MT45W2MW16PAFA85WT
Operating Temperature (max)
85C
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / Rohs Status
Not Compliant
Page Mode READ Operation
mode operation, the address inputs are used to accel-
erate read accesses and cannot be used by the on-chip
circuitry to schedule refresh. If CE# is LOW longer than
the
occur and data may be lost. Page mode should only be
used in systems that can limit CE#-LOW times to less
than 10µs.
Extended WRITE Timing
WRITE operations (see Figure 24 below). An extended
WRITE operation requires that both the write pulse
width (
ened to at least the minimum WRITE cycle time (
[MIN]). These increased timings ensure that time is
available for both a refresh operation and a successful
completion of the WRITE operation.
09005aef80d481d3
AsyncCellularRAM_16_32.fm - Rev. A 2/18/04 EN
When a CellularRAM device is configured for page
Modified timings are required during extended
t
CEM maximum time of 10µs, or no refresh will
t
WP) and the data valid period (
t
DW) be length-
t
WC
ASYNC/PAGE CellularRAM MEMORY
26
Figure 24: Extended WRITE Operation
ADDRESS
DATA-IN
LB#/UB#
Micron Technology, Inc., reserves the right to change products or specifications without notice.
WE#
CE#
2 MEG x 16, 1 MEG x 16
t
CEM or
©2004 Micron Technology, Inc. All Rights Reserved.
t
TM >
t
WP
t
DW
10µs
DATA VALID
>
>
t
WC (MIN)
t
WC (MIN)
ADVANCE