PEF80912HV14NP Lantiq, PEF80912HV14NP Datasheet
PEF80912HV14NP
Specifications of PEF80912HV14NP
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PEF80912HV14NP Summary of contents
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Q-SMINT O 2B1Q Second Gen. Modular ISDN NT (Ordinary) PEF 80912/80913 Version 1.3 Wired Data Sheet March 2001 ...
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Edition March 2001 Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 München, Germany © Infineon Technologies AG 2001. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. ...
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Q-SMINT O 2B1Q Second Gen. Modular ISDN NT (Ordinary) PEF 80912/80913 Version 1.3 Wired ata Sheet 001 ...
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PEF 80912/80913 Revision History: Previous Version: Page Subjects (major changes since last revision) All Editorial changes, addition of notes for clarification etc. Table 1, introduced new version 80913 with extended performance of the U-interface Chapter 1.3 Chapter S-transceiver NT state ...
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Table of Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 3.1.7 Partial Deactivation with U Active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.1.8 ...
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List of Figures Figure 1 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Tables Table 1 NT Products of the 2nd Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 ...
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Overview The PEF 80912 / 80913 (Q-SMINT 8091 [11] and can hence replace the latter in all NT1 applications. Table 1 summarizes the 2nd generation NT products. • Table 1 NT Products of the 2nd Generation PEF80912 PEF80913 PEF81912 ...
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References [1] TS 102 080, Transmission and Multiplexing ; ISDN basic rate access; Digital transmission system on metallic local lines, ETSI, November 1998 [2] T1.601-1998 (Revision of ANSI T1.601-1992), ISDN-Basic Access Interface for Use on Metallic Loops for Application ...
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Second Gen. Modular ISDN NT (Ordinary) ® Q-SMINT O Version 1.3 1.2 Features PEF 80912 Features known from the PEB / PEF 8091 • Single chip solution including U- and S-transceiver • Perfectly suited for the NT1 in ...
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New Features • Reduced number of external components for external U-hybrid required • Optional use 2x20 resistors on the line side of the transformer (e.g. PTCs) • Pin Uref and the according external capacitor removed • ...
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Not Supported are ... • Integrated U-hybrid • ’NT-Star’ with star point on the IOM • The oscillator architecture was changed with respect to the NTC-Q to reduce power consumption consequence, the Q-SMINT can not be connected ...
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Block Diagram • SR1 SR2 SX1 S-Transceiver SX2 TM0 TM1 Test Modes TM2 DIO IOM-2 Interface FSC DCL Figure 2 Block Diagram Data Sheet RST RSTO VDDDET XIN XOUT Clock Generation POR/UVD U/S Transceiver Control DU DD BUS 6 ...
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Pin Definitions and Functions • Table 2 Pin Definitions and Functions Pin Symbol 2 VDDa_UR 1 VSSa_UR 42 VDDa_UX 43 VSSa_UX 36 VDDa_SR 37 VSSa_SR 31 VDDa_SX 30 VSSa_SX 19 VDDD 20 VSSD 8 VDDD 9 VSSD 22 FSC ...
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Table 2 Pin Definitions and Functions (cont’d) Pin Symbol 7 DIO 16 AUA 17 CSO 18 BUS 5 RST 6 RSTO 10 TLL 13 TM0 14 TM1 15 TM2 Data Sheet Type Function I Disable IOM -2: 1: FSC, ...
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Table 2 Pin Definitions and Functions (cont’d) Pin Symbol 28 SX1 29 SX2 32 SR1 33 SR2 40 XIN 39 XOUT 44 AOUT 41 BOUT 3 AIN 4 BIN 34 VDDDET 11 MTI 38 PS1 26 PS2 Data Sheet Type ...
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Table 2 Pin Definitions and Functions (cont’d) Pin Symbol 12 ACT 27 TP1 35 TP2 PU: Internal pull-up resistor (typ. 100 µA) I: Input O: Output (Push-Pull) OD: Output (Open Drain) 1.7.1 Specific Pins LED Pins ACT, LP2I A LED ...
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Note: Optionally, pin ACT can drive a second LED with inverse polarity (connect this additional LED to 3.3 V only). Another LED can be connected to pin LP2I to indicate an active Loopback 2 according to Table 4. Table 4 ...
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System Integration The Q-SMINT O provides NT1 functionality without a microcontroller being necessary. Special selections can be done via pin strapping (CSO, TLL, BUS, etc.). The device has no µP interface. The IOM -2 Interface serves only ...
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Functional Description 2.1 Reset Generation External Reset Input At the RST input an external reset can be applied forcing the Q-SMINT state. This external reset signal is additionally fed to the RSTO output. Reset Ouput If VDDDET is active, ...
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IOM -2 Interface The IOM -2 interface always operates in NT mode according to the IOM Guide [13]. 2.2.1 IOM -2 Functional Description The IOM -2 interface consists of four lines: FSC, DCL, DD, DU. The ...
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U-Transceiver The state machine of the U-Transceiver is based on the NT state machine in the PEB / PEF 8091 documentation [11]. Basic configurations are selected via pin strapping. 2.3.1 2B1Q Frame Structure Transmission on the U 2B1Q is ...
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Table 6 U-Superframe Format Fram- ing Quat 1 – 9 Position s Bit 1 – 18 Position s Super Basic Sync Frame # Frame # Word 1 1 ISW ...
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DEA Deactivation bit – CSO Cold Start Only – UOA U-Only Activation – SAI S-Activity Indicator – FEBE Far-end Block Error – PS1 Power Status Primary Source – PS2 Power Status Secondary Source PS2 = (1) –> Secondary power ...
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U -Deframer 2B1Q (M-bit handling acc. to ETR080 2B1Q Decoding Figure 8 U Deframer - Data Flow Scheme 2B1Q 2.3.2 Cyclic Redundancy Check / FEBE bit An error monitoring function is implemented covering the ...
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C/I Codes The operational status of the U-transceiver is controlled by the Control/Indicate channel (C/I-channel). Table 7 presents all defined C/I codes. An indication is issued permanently by the U-transceiver on DD until a new indication needs to be ...
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DT: Data Through test mode EI1: Error Indication 1 PU: Power-Up RES: Reset SSP: Send Single Pulses test mode TIM: Timing request 2.3.5 State Machine for Line Activation / Deactivation 2.3.5.1 Notation The state machines control the sequence of signals ...
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Standard NT State Machine (IEC-Q / NTC-Q Compatible) • SN0 T14S Pending Timing DC Any State T14S DI SSP or SP C/I= 'SSP' Test DR SN0 Reset Any State DR Pin-RST or ARL C/I= 'RES' T12S SN1 EC-Training AL ...
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Note: The test modes ’Data Through‘ (DT), ‘Send Single Pulses‘ (SSP) and ‘Quiet Mode‘ (QM) can be generated via pins TM0-2 according to If the Metallic Loop Termination is used, then the U-transceiver is forced into the states ‘Reset‘ and ...
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U-Interface Events: ACT = 0/1 ACT-bit received from LT-side. – ACT = 1 requests the U-transceiver to transmit transparently in both directions. In the case of loop-backs, however, transparency in both directions of transmission is established when the receiver is ...
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Outputs of the U-Transceiver: The following signals and indications are issued on IOM U-interface (predefined U-signals): C/I-Indications AI Activation Indication The U-transceiver has established transparency of transmission. The downstream device is requested to establish layer-1 functionality. AIL Activation Indication ...
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Table 9 U-Interface Signals(cont’d) Signal Synch. Word (SW) SN3T present Test Mode 2) SP test signal 1) Note: Alternating ± 3 symbols at 10 kHz. 2) Note: A series of single pulses spaced at intervals of 1.5 ms; alternating +/-3. ...
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BBD0 / BBD0/1 Detected BBD1 These signals are set if either ’1' (BBD1) or ’0' (BBD0) were detected in 4 subsequent basic frames used as a criterion that the receiver has acquired frame synchronization and both its EC- ...
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Outputs denoted with C/I-code output depends on received EOC-command ’LBBD’ according to • Table 12 C/I-Code Output EOC Command received no ’LBBD’ or ’RTN’ after an ’LBBD’ received ’LBBD’ 3) • Outputs denoted with In States ’Pend. Deact. ...
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EC Training The signal SN1 is transmitted on the U-interface to allow the NT-receiver to update the EC-coefficients. The automatic gain control (AGC), the timing recovery and the EQ updating algorithm are disabled. EC-Training 1 The “EC-Training 1” state is ...
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Pending Timing In the NT-mode the pending timing state assures that the C/I-channel code DC is issued four times before entering the ’Deactivated’ state. Receive Reset In state ’Receive Reset’ a reset of the Uk0-receiver is performed, except in case ...
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Metallic Loop Termination For North American applications a maintenance controller according to ANSI T1.601 section 6.5 is implemented. The maintenance pulse stream from the U-interface Metallic Loop Termination circuit (MLT) is fed to pin MTI, usually via an optocoupler. ...
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Pin 1 MTI 0 500 ms Pin 1 MTI 0 500 ms Figure 11 Pulse Streams Selecting Quiet Mode Data Sheet 20 ms < t < 500 ms HIGH 4 ms < ...
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S-Transceiver The S-Transceiver offers the NT state machine described in the User’s Manual V3.4 [10]. The S-transceiver basic configurations are performed via pin strapping. 2.4.1 Line Coding, Frame Structure Line Coding The following figure illustrates the line code. A ...
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Figure 13 Frame Structure at Reference Points S and T (ITU I.430) – F Framing Bit – L. D.C. Balancing Bit – D D-Channel Data Bit – E D-Channel Echo Bit – F Auxiliary Framing Bit A – N ...
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Data Transfer between IOM In the state G3 (Activated) the B1, B2 and D bits are transferred transparently from the S/T to the IOM -2 interface and vice versa. In all other states ’1’s are transmitted to the ...
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IOM-2 Interface C/I code S/T Interface INFO Figure 14 State Diagram Notation As can be seen from the transition criteria, combinations of multiple conditions are possible as well. A “ ” stands for a logical AND combination. And a ...
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Receive Infos on S/T I0 INFO 0 detected I0 Level detected (signal different to I0) I3 INFO 3 detected I3 Any INFO other than INFO 3 Transmit Infos on S/T I0 INFO 0 I2 INFO 2 I4 INFO 4 It ...
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State Machine NT Mode • RST TIM RES DR Reset i0 * RES DC Any State AID RSY ARD i3*ARD G2 Lost Framing S/T i3*AID i2 i3 RSY DR ARD 2) AID RSY RSY G3 Lost Framing U i2 ...
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G1 Deactivated The S-transceiver is not transmitting. There is no signal detected on the S/T-interface, and no activation command is received in the C/I channel. Activation is possible from the S/T interface and from the IOM G1 I0 Detected An ...
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G4 wait for DR Final state after a deactivation request. The S-transceiver remains in this state until DC is issued. Unconditional States Test Mode TM1 Send Single Pulses Test Mode TM2 Send Continuous Pulses C/I Commands • Command Abbr. Deactivation ...
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Command Abbr. Activation Indication AIL Loop Deactivation DC Confirmation Indication Abbr. Timing TIM Receiver not RSY Synchronous Activation Request AR Illegal Code Ciolation CVR Activation Indication AI Deactivation DI Indication • Data Sheet Code Remark 1110 Activation Indication Loop 1111 ...
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Operational Description 3.1 Layer 1 Activation/Deactivation 3.1.1 Complete Activation Initiated by Exchange Figure 16 depicts the procedure if activation has been initiated by the exchange side (LT). • IOM -2 TE S/T-Reference Point INFO INFO ...
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Complete Activation Initiated by TE Figure 17 depicts the procedure if activation has been initiated by the terminal side (TE). • IOM -2 TE S/T-Reference Point INFO INFO 0 TIM PU AR8/10 INFO 1 INFO ...
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Complete Deactivation Figure 18 depicts the procedure if deactivation has been initiated. Deactivation of layer 1 is always initiated by the exchange. • IOM -2 TE S/T-Reference Point INFO INFO 3 INFO 0 RSY DR ...
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Partial Activation Figure 19 depicts the procedure if partial activation has been initiated by the exchange. • IOM -2 TE S/T-Reference Point INFO INFO 0 SBCX-X or IPAC-X Figure 19 Partial Activation Data Sheet Operational ...
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Activation from Exchange with U Active Figure 20 depicts the procedure if activation has been initiated by the exchange with U already being active. • IOM -2 TE S/T-Reference Point INFO INFO 0 INFO 2 ...
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Activation from TE with U Active Figure 21 depicts the procedure if activation has been initiated by the TE with U already being active. • IOM -2 TE S/T-Reference Point INFO INFO 0 TIM PU ...
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Partial Deactivation with U Active Figure 22 depicts the procedure if partial deactivation has been initiated by the exchange; i.e. U remains active. • IOM -2 TE S/T-Reference Point INFO INFO 3 INFO 0 DR ...
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Loop 2 Figure 23 depicts the procedure if loop 2 is closed and opened. • IOM -2 TE S/T-Reference Point INFO 4 AI AR8/10 INFO 3 SBCX-X or IPAC-X Figure 23 Loop 2 Note: Closing / resolving loop ...
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Layer 1 Loopbacks Test loopbacks are specified by the national PTTs in order to facilitate the location of defect systems. Four different loopbacks are defined. The position of each loopback is illustrated in Figure 24. • ® IOM -2 ...
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Loopback No.2 For loopback #2 several alternatives exist. Both the type of loopback and the location may vary. The following loopback types belong to the loopback-#2 category: • complete loopback (B1,B2,D downstream device • B1-channel loopback, always ...
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External Circuitry 3.3.1 Power Supply Blocking Recommendation The following blocking circuitry is suggested. • VDDa_UR VDDa_UX VDDa_SR VDDa_SX VDDD VDDD 1) 100nF VSSD VSSD VSSa_SX VSSa_SR VSSa_UX VSSa_UR 1) These capacitors should be located as near to the pins ...
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AOUT BIN AIN BOUT Figure 26 External Circuitry U-Transceiver U-Transformer Parameters The following Table 14 lists parameters of typical U-transformers: Table 14 U-Transformer Parameters U-Transformer Parameters U-Transformer ratio; Device side : Line side Main inductance of windings on the ...
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Resistors of the External Hybrid R3, R4 and 1 1 9.5 T Resistors on the Line Side R Optional use 2x20 requires compensation resistors ...
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Table 15 S-Transformer Parameters Transformer Parameters Transformer ratio; Device side : Line side Main inductance of windings on the line side Leakage inductance of windings on the line side L Coupling capacitance between the windings on the device side and ...
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Receiver The receiver of the S-transceiver is symmetrical recommended in each receive path preferable to split the resistance into two resistors for each line. This allows to place a high resistance between the transformer and the ...
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Table 16 Crystal Parameters Parameter Frequency Frequency calibration tolerance Load capacitance Max. resonance resistance Max. shunt capacitance Oscillator mode External Components and Parasitics The load capacitance C L capacitances C (pin and PCB capacitances to ground and V Par capacitance ...
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Electrical Characteristics 4.1 Absolute Maximum Ratings • Parameter Ambient temperature under bias Storage temperature Maximum Voltage Maximum Voltage on any pin with respect to ground ESD integrity (according EIA/JESD22-A114B (HBM)): 2 kV Note: Stress above those ...
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DC Characteristics • 3.3 V +/- DDA Digital Parameter Pins All Input low voltage Input high voltage All except Output low voltage DD/DU ACT,LP2I Output high voltage MCLK DD/DU Output low voltage ...
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Requirement ITU-T I.430, chapter 8.5.1.1a): ’At all times except when transmitting a binary zero, the output impedance , in the frequency range of 2kHz to 1 MHz, shall exceed the impedance indicated by the template in Figure 11. The ...
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The signal amplitude measured over a period of 1 min. varies less than 1%. 4.3 Capacitances = 25 °C, 3 • Table 20 Pin Capacitances Parameter Digital pads: Input Capacitance I/O Capacitance Analog ...
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Supply Voltages VDD = + Vdd 5% D VDD = + Vdd 5% A The maximum sinusoidal ripple on VDD is specified in the following figure: • mV (peak) 200 100 10 Figure 30 Maximum Sinusoidal Ripple on Supply ...
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AC Characteristics ° 3 Inputs are driven to 2.4 V for a logical "1" and to 0.4 V for a logical "0". Timing measurements are made at 2.0 V ...
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IOM-2 Interface • DCL t DU/DD (Output) t DU/DD bit n (Output) ® Figure 32 IOM -2 Interface - Bit Synchronization Timing • FSC t 10 DCL Figure 33 IOM-2 Interface - Frame Synchronization Timing • Note: At the ...
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Parameter ® IOM -2 Interface DCL period DCL high DCL low Output data from high impedance to active (FSC high or other than first timeslot) Output data from active to high impedance Output data delay from clock FSC high FSC ...
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Reset Table 21 Reset Input Signal Characteristics Parameter Symbol Length of active t RST low state • RST Figure 34 Reset Input Signal Data Sheet Limit Values min. typ. max DCL clock cycles + 400 ns ...
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Undervoltage Detection Characteristics • HYS V DET V DDmin RSTO Figure 35 Undervoltage Control Timing Data Sheet t t ACT ACT t DEACT 66 PEF 80912/80913 Electrical Characteristics DEACT VDDDET.VSD 2001-03-29 ...
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Table 22 Parameters of the UVD/POR Circuit V = 3.3 V ± Parameter 1) Detection Threshold Hysteresis Max. rising/falling V DD edge for activation/ deactivation of UVD Max. rising V for ...
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Package Outlines Plastic Package, P-MQFT-44 (Metric Quad Flat Package) • • Data Sheet PEF 80912/80913 68 Package Outlines 2001-03-29 ...
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Appendix: Differences between Q- and T-SMINT The Q- and T-SMINT O have been designed compatible as possible. However, some differences between them are unavoidable due to the different line codes 2B1Q and 4B3T used for ...
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U-Transceiver 6.2.1 U-Interface Conformity Table 24 Related Documents to the U-Interface Document ETSI: TS 102 080 ANSI: T1.601-1998 (Revision of ANSI T1.601- 1992) CNET: ST/LAA/ELR/DNP/ 822 RC7355E FTZ-Richtlinie 1 TR 220 Data Sheet Appendix: Differences between Q- and T-SMINT‚O ...
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U-Transceiver State Machines • SN0 T14S Pending Timing Any State T14S SSP or SP C/I= 'SSP' SN0 Any State Pin-RST or ARL C/I= 'RES' SN1 EC-Training AL SN3 Wait for SF AL SN3T Analog Loop Back Pend Receive Res. ...
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T6S T6E T13E T12S U1A Synchronizing RSY SBC Synchronizing LOF AR / ARL Wait for Info U4H LOF AR / ARL U4H U5 U0 Transparent LOF AI / AIL Figure 37 IEC-T/NTC-T Compatible ...
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Command/Indication Codes Table 25 C/I Codes Code Q-SMINT IN 0000 TIM 0001 RES 0010 – 0011 – 0100 EI1 0101 SSP 0110 DT 0111 – 1000 AR 1001 – 1010 ARL 1011 – 1100 AI 1101 – 1110 – ...
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External Circuitry The external circuitry of the Q- and T-SMINT components of the U-transceiver hybrid must be dimensioned different for 2B1Q and 4B3T. All information on the external circuitry is preliminary and may be changed in future documents. • ...
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Table 26 Dimensions of External Components. Component Transformer: Ratio Main Inductivity Resistance R3 Resistance R4 Resistance R T Capacitor C R and R PTC Comp Data Sheet Appendix: Differences between Q- and T-SMINT‚O Q-SMINT O: 2B1Q 1:2 14.5 mH ...
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Index A Absolute Maximum Ratings 57 B Block Diagram 6 C C/I Codes U-Transceiver 19 Cyclic Redundancy Check Characteristics 58 Differences between Q- and T-SMINT 69 E External Circuitry S-Transceiver 53 U-Transceiver 51 F Features 3 ...
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