PEF80902HV11XT Lantiq, PEF80902HV11XT Datasheet
PEF80902HV11XT
Specifications of PEF80902HV11XT
Related parts for PEF80902HV11XT
PEF80902HV11XT Summary of contents
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4B3 din ...
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Edition 2001-11-12 Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 München, Germany © Infineon Technologies AG 2001. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms ...
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4B3 din ...
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PEF 80902 Revision History: Previous Version: Page Subjects (major changes since last revision) Table 10 Additional C/I-command LTD Figure 12 Chapter 2.3.7.4 Chapter 4.2 Input Leakage Current AIN, BIN: max. 30µA Chapter 4.4 Reduced power consumption For questions on technology, ...
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Table of Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 3.1.5 Activation Procedures with Loopback # 3.2 Layer 1 Loopbacks . . ...
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List of Figures Figure 1 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Tables Table 1 NT Products of the 2nd Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 ...
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Overview The PEB 80902 (T-SMINT can hence replace the latter in all NT1 applications. Table 1 on Page 1 summarizes the 2nd generation NT products. • Table 1 NT Products of the 2nd Generation PEF 80902 T-SMINT Package P-MQFP-44 ...
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References [1] TS 102 080, Transmission and Multiplexing; ISDN basic rate access; Digital transmission system on metallic local lines, ETSI, November 1998 [2] FTZ 1 TR 220 Technische Richtlinie, Spezifikation der ISDN Schnittstelle Uk0 Schicht 1, Deutsche Telecom AG, ...
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Second Gen. Modular ISDN NT (Ordinary) ® T-SMINT O Version 1.1 1.2 Features Features known from the PEB 8090 • Single chip solution including U- and S-transceiver • Perfectly suited for the NT1 in the ISDN • Fully automatic ...
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New Features • Optional use of transformers with non-negligible resistance corresponding the line sidePin Vref and the according external capacitor removed • Inputs accept 3.3V and 5V • I/O (open drain) accepts pull-up to 3.3V ...
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Pin Configuration • /VDDDET 35 36 VDDa_SR VSSa_SR 37 38 XOUT 39 XIN 40 BOUT 41 VDDa_UX 42 VSSa_UX 43 AOUT 44 1 Figure 1 Pin Configuration Data Sheet T-SMINTO ...
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Block Diagram • SR1 SR2 SX1 S-Transceiver SX2 TM0 TM1 Test Modes TM2 DIO IOM-2 Interface FSC DCL Figure 2 Block Diagram Data Sheet RST RSTO XIN XOUT VDDDET Clock Generation POR/UVD PEF 80902 Overview U-Tansceiver ...
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Pin Definitions and Functions • Table 2 Pin Definitions and Functions Pin Symbol VDDa_UR 2 VSSa_UR 1 VDDa_UX 42 VSSa_UX 43 VDDa_SR 36 VSSa_SR 37 VDDa_SX 31 VSSa_SX 30 VDDD 19 VSSD 20 VDDD 8 VSSD 9 FSC 22 ...
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Table 2 Pin Definitions and Functions (cont’d) Pin Symbol DU 24 DIO 7 BUS 18 RST 5 RSTO 6 TM0 13 TM1 14 TM2 15 SX1 28 SX2 29 SR1 32 SR2 33 XIN 40 XOUT 39 Data Sheet Type ...
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Table 2 Pin Definitions and Functions (cont’d) Pin Symbol AOUT 44 BOUT 41 AIN 3 BIN 4 VDDDET 34 ACT 12 TP1 27 TP2 35 10,11, 16,17, 26,38 PU: Internal pull-up resistor (typ. 100µA) I: Input O: Output (Push-Pull) OD: ...
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Table 3 ACT States Pin ACT LED V OFF DD 2Hz (1 : 1)* fast flashing 1Hz (3 : 1)* slow flashing 0 GND ON Note: * denotes the duty cycle ’high’ : ’low’. with: U_Deactivated: ’Deactivated State’ as defined ...
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Table 5 Test Modes (cont’d) TM0 TM1 TM2 The S-transceiver transmits pulses with alternating polarity at a rate of 192 kHz resulting kHz envelope. ...
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S/T - Interface Figure 3 Application Example T-SMINT Data Sheet DC/DC-Converter IDCC PEB2023 T-SMINTO S PEF80902 IOM-2 LEDs Pin Strap - Mode Selection - Loop 2 Ind. - Disable IOM - 2 - Activation - ...
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Functional Description 2.1 Reset Generation External Reset Input At the RST input an external reset can be applied forcing the T-SMINT state. This external reset signal is additionally fed to the RSTO output. Reset Ouput If VDDDET is active, ...
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IOM -2 Interface â The IOM -2 interface always operates in NT mode according to the IOM Guide [12]. â 2.2.1 IOM -2 Functional Description â The IOM -2 interface consists of four lines: FSC, DCL, DD, DU. The ...
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U-Transceiver The statemachine of the U-Transceiver is compatible to the NT state machine in the PEB 8090 documentation [9], but includes some minor changes for simplification and compliance to Ref. [1]. Basic configurations are selected via pin strapping 2.3.1 ...
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Barker code for both symbol and frame synchronization (not scrambled) • 1 symbol: Ternary maintenance symbol (not scrambled) The 108 user data symbols are split into four equally structured groups. Each group (27 ternary symbols, resp. 36 ...
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D ... D Ternary data of IOM Maintenance symbol +, – Syncword Data Sheet Functional Description ® -2 frames 1 ... 8 17 PEF 80902 2001-11-12 ...
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Table 7 Frame Structure B for Upstream Transmission 1/2 1/2 1 ...
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Maintenance Channel The 4B3T frame structure provides a 1 kbit/s M(aintenance)-channel for the transfer of remote loopback commands and error indications. Loopback Commands The LT station uses the M-channel to request remote loopbacks. Loopback commands are coded with a ...
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Table 8 MMS 43 Coding Table (cont’ – ...
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Table 9 4B3T Decoding Table (cont’ – 0 – – – 2.3.4.1 Monitoring of Code Violations The running digital sum monitor (RDSM) computes the running digital sum from the received ...
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Command/Indication Codes Both commands and indications depend on the data direction. defined C/I codes. A new command or indication will be recognized as valid after it has been detected in two successive IOM Indications are strictly state orientated. Refer ...
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DC Deactivation Confirmation 2.3.7 State Machine for Activation and Deactivation 2.3.7.1 State Machine Notation The following state diagram describes all the actions/reactions resulting from any command or detected signal and resulting from the various operating modes. The states with its ...
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The state machines are designed to cope with all ISDN devices with IOM interfaces. Undefined situations are excluded. In any case, the involved devices will enter defined conditions as soon as the line is deactivated. 2.3.7.2 Awake Protocol For the ...
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Acting as Calling Station After sending the awake signal, the awaking U-transceiver waits for the acknowledge. After 12 ms, the awake signal is repeated acknowledge has been recognized acknowledge signal has been recognized, the U-transceiver waits ...
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NT State Machine (IEC-T / NTC-T Compatible) • T6S T6E T13E Ack. Sent / Received T12S U1A (U0 & T12E) Synchronizing RSY SBC Synchronizing LOF AR / ARL Wait for Info U4H LOF ...
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Table 11 Differences to the former NT-SM of the IEC-T/NTC-T No. State/ Signal Change 1. State ’Deact. split into 3 states Request Rec.’ - ’Pend. Deactivation 1’ - ’Reset’ State - ’Test’ State 2. State ’Loss of new inserted, ...
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LTD LT Disable This unconditional command forces the U-transceiver to state ’Test’, where it transmits U0. No further action is initiated. RES Reset Unconditional command which resets the U-transceiver. SSP Send Single Pulses Unconditional command which requests the transmission of ...
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Table 12 Timers (cont’d) Timer Duration (ms) T12 12 T13 13 2.3.7.5 Outputs of the U-Transceiver Below the signals and indications are summarized that are issued on IOM indications) and on the U-interface (predefined U-signals). C/I Indications AI Activation Indication ...
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Signals on U-Interface The signals U0, U1W, U1A, U1, U3, U5 and SP are transmitted on the U-interface.They are defined in Table 17. ® Signals on IOM -2 The Data (B+B+D) is set to all ’1’s in all states besides ...
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Acknowledge Sent / Receive After having sent the awake signal, the U-transceiver has received the acknowledge wake tone. If being awoken the U-transceiver has sent the acknowledge. In both cases the U-transceiver waits for possible repetition or time-out. Awake Signal ...
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Start Awaking Uk0 On the receipt the C/I-channel the U-transceiver sends the awake signal U1W to start an activation. Synchronizing After the successful awake procedure the U-transceiver trains its receiver coefficients until it is able to detect ...
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S-Transceiver The S-Transceiver offers the NT state machine described in the User’s Manual V3.4 [8]. The S-transceiver basic configurations are performed via pin strapping. 2.4.1 Line Coding, Frame Structure Line Coding The following figure illustrates the line code. A ...
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Figure 10 Frame Structure at Reference Points S and T (ITU I.430) – F Framing Bit – L. D.C. Balancing Bit – D D-Channel Data Bit – E D-Channel Echo Bit – F Auxiliary Framing Bit A – N ...
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Data Transfer between IOM In the state G3 (Activated) the B1, B2 and D bits are transferred transparently from the â S/T to the IOM -2 interface and vice versa. In all other states ’1’s are transmitted to the ...
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IOM-2 Interface C/I code S/T Interface INFO Figure 11 State Diagram Notation As can be seen from the transition criteria, combinations of multiple conditions are possible as well. A “ ” stands for a logical AND combination. And a ...
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I0 Level detected (signal different to I0) I3 INFO 3 detected I3 Any INFO other than INFO 3 Transmit Infos on S/T I0 INFO 0 I2 INFO 2 I4 INFO 4 It Send Single Pulses (TM1). Send Continuous Pulses (TM2). ...
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State Machine NT Mode • RST TIM RES DR Reset i0 * RES DC Any State AID RSY ARD i3*ARD G2 Lost Framing S/T i3*AID i2 i3 RSY DR ARD 2) AID RSY RSY G3 Lost Framing U i2 ...
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G1 Deactivated The S-transceiver is not transmitting. There is no signal detected on the S/T-interface, and no activation command is received in the C/I channel. Activation is possible from the S/T interface and from the IOM G1 I0 Detected An ...
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G4 wait for DR Final state after a deactivation request. The S-transceiver remains in this state until DC is issued. Unconditional States Test Mode TM1 Send Single Pulses Test Mode TM2 Send Continuous Pulses C/I Commands • Command Abbr. Deactivation ...
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Command Abbr. Activation Indication AIL Loop Deactivation DC Confirmation Indication Abbr. Timing TIM Receiver not RSY Synchronous Activation Request AR Illegal Code Ciolation CVR Activation Indication AI Deactivation DI Indication • Data Sheet Code Remark 1110 Activation Indication Loop 1111 ...
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Operational Description 3.1 Layer 1 Activation/Deactivation 3.1.1 Generation of 4B3T Signal Elements For control and monitoring purposes of the activation/deactivation progress the following signal elements are defined by TS 102 080 and FTZ 1 TR 220. Table 17 4B3T ...
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Table 17 4B3T Signal Elements (cont’ indicates that the whole link to the TE is synchronous in both directions. On detecting U3 the LT requests the NT by U4H to establish a fully transparent connection. The M-channel on ...
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Table 18 Generation of the 4B3T Signal Elements (cont’d) U4H Table 19 S/T-Interface Signals Signals from INFO 0 No signal. INFO 2 Frame with all bits and D-echo ...
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Complete Activation Initiated by Exchange • IOM â S/T-Reference Point INFO INFO 0 INFO 2 AR INFO 3 INFO 4 AI AR8/10 SBCX-X or IPAC-X Figure 13 Activation Initiated by Exchange Note: The LT ...
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Complete Activation Initiated by TE • â IOM -2 TE S/T-Reference Point INFO INFO 0 TIM PU AR8/10 INFO 1 INFO 2 RSY INFO 0 AR INFO 3 INFO 4 AI SBCX-X or IPAC-X Figure 14 ...
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Deactivation • â IOM -2 TE S/T-Reference Point INFO INFO 3 INFO 0 RSY DR INFO SBCX-X or IPAC-X Figure 15 Deactivation (always Initiated by LT) Data Sheet Operational Description NT U-Reference Point ...
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Activation Procedures with Loopback #2 • â IOM -2 TE S/T-Reference Point INFO 4 AI AR8/10 INFO 3 SBCX-X or IPAC-X Figure 16 Activation of Loopback #2 Note: Closing/resolving loop 2 may provoke the S-transceiver to resynchronize. In this ...
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Layer 1 Loopbacks Test loopbacks are specified by the national PTTs in order to facilitate the location of defect systems. Four different loopbacks are defined. The position of each loopback is illustrated in Figure 17. • IOM ® -2 ...
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External Circuitry 3.3.1 Power Supply Blocking Recommendation The following blocking circuitry is suggested. • VDDa_UR VDDa_UX VDDa_SR VDDa_SX VDDD VDDD 1) 100nF VSSD VSSD VSSa_SX VSSa_SR VSSa_UX VSSa_UR 1) These capacitors should be located as near to the pins ...
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AOUT BIN AIN BOUT Figure 19 External Circuitry U-Transceiver with External Hybrid U-Transformer Parameters The following table lists parameters of typical U-transformers. Table 20 U-Transformer Parameters U-Transformer Parameters U-Transformer ratio; Device side : Line side Main inductanc of windings ...
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Resistors of the External Hybrid R3, R4 and 1. 1 Resistors COMP T • Optional use of trafos with non negligible resistance R resistors R depending ...
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S-Transformer Parameters The following Table 21 lists parameters of a typical S-transformer: Table 21 S-Transformer Parameters Transformer Parameters Transformer ratio; Device side : Line side Main inductance of windings on the line side Leakage inductance of windings on the line ...
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SX1 SX2 Figure 20 External Circuitry S-Interface Transmitter Receiver The receiver of the S-transceiver is symmetrical recommended in each receive path preferable to split the resistance into two resistors for each line. This allows to ...
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Oscillator Circuitry Figure 22 illustrates the recommended oscillator circuit. • Figure 22 Crystal Oscillator Table 22 Crystal Parameters Parameter Frequency Frequency calibration tolerance Load capacitance Max. resonance resistance Max. shunt capacitance Oscillator mode External Components and Parasitics The load ...
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Electrical Characteristics 4.1 Absolute Maximum Ratings • Parameter Ambient temperature under bias Storage temperature Maximum Voltage Maximum Voltage on any pin with respect to ground ESD integrity (according EIA/JESD22-A114B (HBM)): 2 kV Note: Stress above those ...
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DC Characteristics • 3.3 V +/- DDA Digital Parameter Pins All Input low voltage Input high voltage All except Output low voltage DD/DU ACT,LP2I Output high voltage MCLK DD/DU Output low voltage ...
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Requirement ITU-T I.430, chapter 8.5.1.1a): ’At all times except when transmitting a binary zero, the output impedance , in the frequency range of 2kHz to 1 MHz, shall exceed the impedance indicated by the template in Figure 11. The ...
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Capacitances = 25 °C, 3 • Table 26 Pin Capacitances Parameter Digital pads: Input Capacitance I/O Capacitance Analog pads: Load Capacitance 4.4 Power Consumption • Power Consumption VDD=3.3 V, VSS=0 V, Inputs at ...
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Figure 23 Maximum Sinusoidal Ripple on Supply Voltage Data Sheet Electrical Characteristics 60 80 100 Frequency / kHz Frequency Ripple 60 PEF 80902 ITD04269.vsd 2001-11-12 ...
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AC Characteristics ° 3 Inputs are driven to 2.4 V for a logical "1" and to 0.4 V for a logical "0". Timing measurements are made at 2.0 V ...
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IOM-2 Interface • DCL t DU/DD (Output) t DU/DD bit n (Output) ® Figure 25 IOM -2 Interface - Bit Synchronization Timing • FSC t 10 DCL Figure 26 IOM-2 Interface - Frame Synchronization Timing • Note: At the ...
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Parameter ® IOM -2 Interface DCL period DCL high DCL low Output data from high impedance to active (FSC high or other than first timeslot) Output data from active to high impedance Output data delay from clock FSC high FSC ...
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Reset Table 27 Reset Input Signal Characteristics Parameter Symbol Length of active t RST low state • RST Figure 27 Reset Input Signal Data Sheet Limit Values min. typ. max DCL clock cycles + 400 ns ...
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Undervoltage Detection Characteristics • HYS V DET V DDmin RSTO Figure 28 Undervoltage Control Timing Table 28 Parameters of the UVD/POR Circuit V = 3.3 V ± ...
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V = 3.3 V ± Parameter Delay for activation of RSTO Delay for deactivation of RSTO 1) The Detection Threshold V DET ® T-SMINT . Therefore, the board designer must take ...
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Package Outlines Plastic Package, P-MQFP-44 (Metric Quad Flat Package) • • Data Sheet 67 PEF 80902 Package Outlines 2001-11-12 ...
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Appendix: Differences between Q- and T-SMINT â The Q- and T-SMINT O have been designed compatible as possible. However, some differences between them are unavoidable due to the different line codes 2B1Q and 4B3T used for ...
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Table 30 ACT States (cont’d) LED States slow flashing on Note: * denotes the duty cycle ’high’ : ’low’. 6.2 U-Transceiver 6.2.1 U-Interface Conformity • Table 31 Related Documents to the U-Interface ETSI: TS 102 080 ANSI: T1.601-1998 (Revision of ...
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U-Transceiver State Machines • SN0 T14S Pending Timing Any State T14S SSP or SP C/I= 'SSP' SN0 Any State Pin-RST or ARL C/I= 'RES' SN1 EC-Training AL SN3 Wait for SF AL SN3T Analog Loop Back Pend Receive Res. ...
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T6S T6E T13E Ack. Sent / Received T12S U1A (U0 & T12E) Synchronizing RSY SBC Synchronizing LOF AR / ARL Wait for Info U4H LOF AR / ARL U4H U0 U5 Transparent LOF ...
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Command/Indication Codes Table 32 C/I Codes Code Q-SMINT IN 0000 TIM 0001 RES 0010 – 0011 – 0100 EI1 0101 SSP 0110 DT 0111 – 1000 AR 1001 – 1010 ARL 1011 – 1100 AI 1101 – 1110 – ...
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External Circuitry The external circuitry of the Q- and T-SMINT components of the U-transceiver hybrid must be dimensioned different for 2B1Q and 4B3T. All information on the external circuitry is preliminary and may be changed in future documents. • ...
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Index A Absolute Maximum Ratings 56 B Block Diagram 6 C C/I Codes U-Transceiver Characteristics 57 Differences between Q- and T-SMINT 68 E External Circuitry S-Transceiver 52 U-Transceiver 50 F Features 3 I IOM®-2 Interface AC ...
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