PEF20550HV2.1XT Infineon Technologies, PEF20550HV2.1XT Datasheet - Page 128
PEF20550HV2.1XT
Manufacturer Part Number
PEF20550HV2.1XT
Description
Manufacturer
Infineon Technologies
Datasheet
1.PEF20550HV2.1XT.pdf
(407 pages)
Specifications of PEF20550HV2.1XT
Lead Free Status / Rohs Status
Compliant
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4.5
Access in demultiplexed P-interface mode:
Access in multiplexed P-interface mode:
Reset value: XF
VN(3:0)
ECMD2
Semiconductor Group
bit 7
VN3
ELIC
ELIC-Version Number according to the following table:
VN (3:0)
1111
1110
1101
ELIC CFI-Mode Bit 2.
If set to ’0’, the CFI-mode 0 with a 2.048-MBit/s data rate can be used with a
2.048-MHz PDC-input clock.
This mode requires further restrictions of the current ELIC-specification:
1) EPIC-1 PMOD:PCR must be set to ’1’.
2) EPIC-1 CMD2:COC must be programmed to ’0’, i.e. it is not possible to
3) EPIC-1 CMD1:CSS must be programmed to ’0’, i.e. it is not possible to
4) The timing of the PCM-interface is expanded:
®
VN2
Note: Although the PCM clock PDC is set to double clock rate by this bit,
output a DCL-clock with a frequency of twice the CFI-data rate.
select DCL as clock and FSC as framing signal source for the
configurable interface.
Parameter
Clock period
Clock period low
Clock period high
Mode Register / Version Number Register (EMOD)
H
the data rate must always be equal to the clock rate.
VN1
Symbol Limit Values Unit Test Condition
T
T
T
CP
CPL
CPH
VN0
128
min.
480
200
200
1
ELIC-Version
V 1.1
V 1.2
V 1.3
read/write
read/write
max.
–
–
–
Detailed Register Description
1
ns
ns
ns
address: 3F
EMOD:ECMD2 = '0'
address: 7E
ECMD2
PEB 20550
PEF 20550
bit 0
H
H
DMXAD
01.96
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