PEF20550HV2.1XT Infineon Technologies, PEF20550HV2.1XT Datasheet - Page 138
PEF20550HV2.1XT
Manufacturer Part Number
PEF20550HV2.1XT
Description
Manufacturer
Infineon Technologies
Datasheet
1.PEF20550HV2.1XT.pdf
(407 pages)
Specifications of PEF20550HV2.1XT
Lead Free Status / Rohs Status
Compliant
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FC2..0
4.6.8
Access in demultiplexed P-interface mode:
Access in multiplexed P-interface mode:
Reset value: 00
Semiconductor Group
bit 7
FC2
Configurable Interface Mode Register 2 (CMD2)
Framing output Control.
Given that CMD1:CSS = 0, these bits determine the position of the FSC-
pulse relative to the CFI-frame, as well as the type of FSC-pulse generated.
The position and width of the FSC-signal with respect to the CFI-frame can
be found in the following two figures 56 and 57.
FC1
H
FC0
COC
138
CXF
read/write
read/write
Detailed Register Description
CRR
address: 17
address: 2E
CBN9
PEB 20550
PEF 20550
bit 0
H
H
CBN8
01.96
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