PEF20550HV2.1XT Infineon Technologies, PEF20550HV2.1XT Datasheet - Page 198
PEF20550HV2.1XT
Manufacturer Part Number
PEF20550HV2.1XT
Description
Manufacturer
Infineon Technologies
Datasheet
1.PEF20550HV2.1XT.pdf
(407 pages)
Specifications of PEF20550HV2.1XT
Lead Free Status / Rohs Status
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63
65
67
69
62
64
66
68
61
60
59
58
70
71
PMOD
5.2
5.2.1
5.2.1.1 PCM Interface Signals
The PCM interface signals are summarized in table 23.
Table 23
Signals at the PCM Interface
Pin No.
5.2.1.2 PCM Interface Registers
The characteristics at the PCM interface (timing, modes of operation, etc. … ) are
programmed in the 4 PCM interface registers and in the Operation Mode Register
OMDR. The function of each bit is described in chapter 5.2.1.3. For addresses, refer to
chapter 4.1.
PCM Mode Register
Semiconductor Group
Configuration of Interfaces
PCM Interface Configuration
bit 7
PMD1
Symbol
TxD0
TxD1
TxD2
TxD3
TSC0
TSC1
TSC2
TSC3
RxD0
RxD1
RxD2
RxD3
PFS
PDC
PMD0
I: Input
O: Output
O
O
O
O
O
O
O
O
I
I
I
I
I
I
PCR
Function
Transmit PCM interface data: serial data is sent at
standard TTL or CMOS levels (tristate drivers).
These pins can be set to high impedance with a
2 bit resolution.
Tristate control signals for the PCM transmit lines.
These signals are low when the corresponding
TxD# outputs are valid.
Receive PCM interface data: serial data is
received at standard TTL or CMOS levels.
PCM interface frame synchronization signal.
PCM interface data clock, single or double rate.
PSM
198
read/write
AIS1
AIS0
reset value:
Application Hints
AIC1
PEB 20550
PEF 20550
bit 0
00
AIC0
H
01.96
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