PEF20550HV2.1XT Infineon Technologies, PEF20550HV2.1XT Datasheet - Page 236
PEF20550HV2.1XT
Manufacturer Part Number
PEF20550HV2.1XT
Description
Manufacturer
Infineon Technologies
Datasheet
1.PEF20550HV2.1XT.pdf
(407 pages)
Specifications of PEF20550HV2.1XT
Lead Free Status / Rohs Status
Compliant
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Table 35 shows the function taken over by each of the CFI interface pins, depending on
the CFI mode and the values programmed to CIS1 and CIS0.
Table 35
CFI Pin Configuration
CFI
Mode
0
1
2
3
Figure 82 shows the correlation between physical and logical CFI ports in CFI modes 0,
1, 2 and 3:
Figure 82
Correlation Between Physical and Logical CFI Ports
Semiconductor Group
DU0
IN0
IN0
CIS0 = 0
IN
CIS0 = 0
I/O4
Port 0
DD0
OUT0
OUT0
OUT
I/O0
DU1
IN1
IN1
CIS1 = 0
–
I/O5
Port 1
DD1
OUT1
OUT1
high Z
I/O1
236
I/O6
DU2
IN2
IN0
CIS0 = 1
IN
CIS0 = 1
Port 2
DD2
OUT2
high Z
high Z
I/O2
DU3
IN3
IN1
CIS1 = 1
–
I/O7
Application Hints
Port 3
PEB 20550
PEF 20550
DD3
OUT3
high Z
high Z
I/O3
01.96
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