PEF20550HV2.1XT Infineon Technologies, PEF20550HV2.1XT Datasheet - Page 263
PEF20550HV2.1XT
Manufacturer Part Number
PEF20550HV2.1XT
Description
Manufacturer
Infineon Technologies
Datasheet
1.PEF20550HV2.1XT.pdf
(407 pages)
Specifications of PEF20550HV2.1XT
Lead Free Status / Rohs Status
Compliant
- Current page: 263 of 407
- Download datasheet (2Mb)
Downstream: CFI port 4, timeslot 2, bits 7 … 0 from PCM port 1, timeslot 3, bits 7 … 0
The following sequence sets transmit timeslot 12 of PCM port 0 to low impedance:
Examples
In PCM mode 1 and CFI mode 3 the following connections shall be programmed:
Upstream: CFI port 5, timeslot 7, bits 7 … 0 to PCM port 0, timeslot 12, bits 7 … 0
Semiconductor Group
W:MADR = 1001 1000
W:MAAR
W:MACR = 0111 0001
W:MADR = 0000 0111
W:MAAR
W:MACR = 0111 0001
W:MADR =
W:MAAR
W:MACR =
= 1011 1011
= 0001 1000
= 1001 1011
0000 1111
0110 0000
B
B
B
B
B
B
B
B
B
; PCM timeslot encoding according to figure 84
; CFI timeslot encoding according to figure 84
; CM code for switching a 64 kBit/s channel
; PCM timeslot encoding according to figure 84
; CFI timeslot encoding according to figure 84
; CM code for switching a 64 kBit/s channel (0001)
; all bits to low Z
; PCM timeslot encoding according to figure 84
; MOC code ‘1100’ to access the tristate field
(code ‘0001’)
263
Application Hints
PEB 20550
PEF 20550
01.96
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