PEF20550HV2.1XT Infineon Technologies, PEF20550HV2.1XT Datasheet - Page 288
PEF20550HV2.1XT
Manufacturer Part Number
PEF20550HV2.1XT
Description
Manufacturer
Infineon Technologies
Datasheet
1.PEF20550HV2.1XT.pdf
(407 pages)
Specifications of PEF20550HV2.1XT
Lead Free Status / Rohs Status
Compliant
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After these programming steps, the control memory will have the following content:
Figure 101
Control Memory Contents for Decentral D-Channel Handling
Central D-Channel Handling Scheme
This option applies for IOM channels where the even timeslot consists of an 8 bit monitor
channel and the odd timeslot of a 2 bit D-Channel followed by a 4 bit C/I channel followed
by the 2 monitor handshake bits MR and MX.
The monitor channel is handled by the MF handler according to the selected protocol,
handshake or non-handshake. If the handshake option is selected (IOM-2), the MF
handler controls the MR and MX bits according to the IOM-2 specification. If the non-
handshake option is selected (IOM-1), the MF handler sets both MR and MX bits to
Semiconductor Group
Up-
stream
Down-
stream
CFI
Frame
0
127
0
127
P0, TS2
P0, TS3
P0, TS2
P0, TS3
0
1
1
1
Code Field
0
0
0 0
0 1
288
0
0
0
0
0
1
Control Memory
X
X
1
1
X X X X X X X
X
1
1
X
1
0
C/I Value
C/I Value
Data Field
X
0
1
X
1
0
X
0
1
Application Hints
ITD08080
X
1
1 1
X
1
PEB 20550
PEF 20550
01.96
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