PEF20550HV2.1XT Infineon Technologies, PEF20550HV2.1XT Datasheet - Page 330
PEF20550HV2.1XT
Manufacturer Part Number
PEF20550HV2.1XT
Description
Manufacturer
Infineon Technologies
Datasheet
1.PEF20550HV2.1XT.pdf
(407 pages)
Specifications of PEF20550HV2.1XT
Lead Free Status / Rohs Status
Compliant
- Current page: 330 of 407
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2) In PCM mode 0 and CFI mode 0, the P shall have access to both the downstream
Wait for next SIN interrupt and transfer further data bytes … .
Examples
1) In PCM mode 0, the synchronous transfer utility (channel A) shall be used to loop
Semiconductor Group
bits 7 … 6 of downstream PCM port 1, timeslot 5 back to bits 7 … 6 of upstream
PCM port 2, timeslot 9. Since no P access to the data is required the ISTA_E:SIN
and SOV bits are both masked:
W:MASK
W:SARA
W:SAXA
W:STCR
and upstream CFI port 0, timeslot 1 via the synchronous transfer channel B:
W:SARB
W:SAXB
W:STCR
Wait for interrupt:
R:ISTA
R:SADB
W:SADB
= downstream CFI data
= 03
= 13
= 25
= 47
= 81
= 81
= 88
= 02
= upstream CFI data
H
H
H
H
H
H
H
H
; SIN = SOV = 1
; ISRA = 0, port 1, TS5
; ISXA = 0, port 2, TS9
; TAE = 1, CTA2 … 0 = 111 (bits 7 … 6)
; ISRB = 1, port 0, TS1
; ISXB = 1, port 0, TS1
; TBE = 1, CTA2 … 0 = 001 (bits 7 … 0)
; SIN = 1
330
Application Hints
PEB 20550
PEF 20550
01.96
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