PEF20550HV2.1XT Infineon Technologies, PEF20550HV2.1XT Datasheet - Page 336
PEF20550HV2.1XT
Manufacturer Part Number
PEF20550HV2.1XT
Description
Manufacturer
Infineon Technologies
Datasheet
1.PEF20550HV2.1XT.pdf
(407 pages)
Specifications of PEF20550HV2.1XT
Lead Free Status / Rohs Status
Compliant
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used to supervise the clock and framing signals for missing or additional clock cycles.
The ELIC internally checks the PFS period against the duration expected from the
programmed clock rate. The clock rate corresponds to the frequency applied to the PDC
pin. The number of clock cycles received within one PFS period is compared with the
values programmed to PBNR (number of bits per frame) and PMOD:PCR (single/double
clock rate operation). If for example single clock rate operation with 24 timeslots per
frame is programmed, the ELIC expects 192 clock cycles within one PFS period. The
synchronous state is reached after the ELIC has detected two consecutive correct
frames. The synchronous state is lost if one erroneous frame is found. The
Figure 114
Connection of Redundant PCM Transmission Lines to the ELIC
5.8.3
Usually the repetition rate of the applied framing pulse PFS is identical to the frame
period (125 s). If this is the case, the ’loss of synchronism indication function’ can be
Semiconductor Group
EPIC
OUT0
TSC0
IN0
PMOD AIS0
ISTA PIM
R
PCM Framing Supervision
:
:
Logical Ports
=1
1
0
Physical Pins:
TXD0
TSC0
RXD0
RXD1
TSC1
336
Line Drivers
& Receivers
®
Application Hints
PCM Transmission
Line #1
PCM Transmission
Line #2
PEB 20550
PEF 20550
ITD08094
01.96
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