PEF20550HV2.1XT Infineon Technologies, PEF20550HV2.1XT Datasheet - Page 356
PEF20550HV2.1XT
Manufacturer Part Number
PEF20550HV2.1XT
Description
Manufacturer
Infineon Technologies
Datasheet
1.PEF20550HV2.1XT.pdf
(407 pages)
Specifications of PEF20550HV2.1XT
Lead Free Status / Rohs Status
Compliant
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6.1.2
This part of the Application Note modifies the initialization example of the ELIC Technical
Manual to interface two digital IOM-2 subscribers to a 2 Mbit PCM 30 switching network.
As shown below, the ELIC is configured to accept a 4 MHz clock as PDC and HDCB
input and to output a CFI clock and frame sync.
Figure 124
Principal ELIC
Semiconductor Group
Basic Initialization
FSC
DCL
IOM -2
(LC)
R
®
Interfaces
D Channel Arbiter
SACCO A
SACCO B
EPIC
R
356
HDCB
HFSB
RXDB/TXDB
8 kHz
4 kHz
Application Notes
ITS08104
PEB 20550
PEF 20550
PDC
PCM
PFS
30
01.96
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