PEF20550HV2.1XT Infineon Technologies, PEF20550HV2.1XT Datasheet - Page 60
PEF20550HV2.1XT
Manufacturer Part Number
PEF20550HV2.1XT
Description
Manufacturer
Infineon Technologies
Datasheet
1.PEF20550HV2.1XT.pdf
(407 pages)
Specifications of PEF20550HV2.1XT
Lead Free Status / Rohs Status
Compliant
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If the data transfer is initiated via the proper command, the SACCO automatically
requests the correct amount of block data transfers (n
by activating the DRQT-line.
Refer to chapter 2.2.7.2 for a detailed description of the DMA transfer timing.
2.2.7.4 Protocol Support
The SACCO supports the following fundamental HDLC functions:
– Flag insertion/deletion,
– Bit stuffing,
– CRC-generation and checking,
– Address recognition.
Further more it provides six different operating modes, which can be set via the MODE
register. These are:
– Auto Mode,
– Non-Auto Mode,
– Transparent Mode 0 and 1,
– Extended Transparent Mode 0 and 1.
These modes provide different levels of HDLC processing. An overview is given in
figure 35.
.
Figure 35
Support of the HDLC Protocol by the SACCO
Semiconductor Group
Flag
SACCO
User
Address
Control
I-
Field
60
CRC
32 + remainder, n = 0, 1, 2, …)
Flag
ITD08035
Functional Description
Auto Mode
Non-Auto Mode
Transparent Mode 1
Transparent Mode 0
Extended Transparent
Mode
PEB 20550
PEF 20550
01.96
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