PEF20550HV2.1XT Infineon Technologies, PEF20550HV2.1XT Datasheet - Page 61
PEF20550HV2.1XT
Manufacturer Part Number
PEF20550HV2.1XT
Description
Manufacturer
Infineon Technologies
Datasheet
1.PEF20550HV2.1XT.pdf
(407 pages)
Specifications of PEF20550HV2.1XT
Lead Free Status / Rohs Status
Compliant
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Depending on the operating mode the following combinations are considered valid
addresses:
Table 8
Address Recognition
Operating
Mode
Auto-mode,
2-byte
address field
Auto-mode,
1-byte
address field
Non-auto
mode,
2-byte
address field
Address Recognition
Address recognition is performed in three operating modes (auto-mode, non-auto-mode
and transparent mode 1). Two pairs of compare registers (RAH1, RAH2: high byte
compare, RAL1, RAL2: low byte compare) are provided. RAL2 may be used for a
broadcast address. In auto-mode and non-auto-mode 1- or 2-byte address fields are
supported, transparent mode 1 is restricted on high byte recognition. The high byte
address is additionally compared with the LAPD group address (FC
Semiconductor Group
Compare
Value
High Byte
<RAH1>
<RAH2>
FCH
FEH
<RAH1>
<RAH2>
FCH
FEH
–
–
<RAH1>
<RAH2>
FCH
FEH
<RAH1>
<RAH2>
FCH
FEH
Compare
Value
Low Byte
<RAL1>
<RAL1>
<RAL1>
<RAL1>
<RAL2>
<RAL2>
<RAL2>
<RAL2>
<RAL1>
<RAL2>
<RAL1>
<RAL1>
<RAL1>
<RAL1>
<RAHL2>
<RAL2>
<RAL2>
<RAL2>
Activity
Processed, following the auto-mode protocol
Frame is stored transparently in RFIFO
Processed, following the auto-mode protocol
Frame is stored transparently in RFIFO
Frame is stored transparently in RFIFO
61
Functional Description
H
, FE
H
PEB 20550
).
PEF 20550
01.96
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