PRIXP425ABD Intel, PRIXP425ABD Datasheet - Page 31

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PRIXP425ABD

Manufacturer Part Number
PRIXP425ABD
Description
Manufacturer
Intel
Datasheet

Specifications of PRIXP425ABD

Core Operating Frequency
533MHz
Package Type
BGA
Pin Count
492
Mounting
Surface Mount
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Lead Free Status / Rohs Status
Compliant

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Datasheet—Intel
Table 5.
Table 6.
3.1
June 2007
Document Number:
Signal Type Definitions (Sheet 2 of 2)
Processors’ Signal Interface Summary Table
Pin Description Tables
This section identifies all the signal pins by symbol name, type and description. Names
should follow the following convention, all capital letters with a trailing “_N” indicate a
signal is asserted when driven to a logic low (digital 0). The description includes the full
name of the pin along with a functional description. This section does not specify the
number of power and ground pins required, but does include the number of different
types of power pins required.
A signal called active high specifies that the interface is active when driven to a logic 1
and inactive when driven to a logic 0.
A signal called active low specifies that the interface is active when driven to a logic 0
and inactive when driven to a logic 1.
®
Table 7, “SDRAM Interface” on page 33
Table 8, “PCI Controller” on page 34
Table 9, “High-Speed, Serial Interface 0” on page 36
Table 10, “High-Speed, Serial Interface 1” on page 37
Table 11, “MII Interfaces” on page 38
Table 12, “UTOPIA Level 2 Interface” on page 40
Table 13, “Expansion Bus Interface” on page 41
Table 14, “UART Interfaces” on page 42
Table 15, “USB Interface” on page 43
Table 16, “Oscillator Interface” on page 44
Table 17, “GPIO Interface” on page 44
Table 18, “JTAG Interface” on page 45
Table 19, “System Interface††” on page 45
Table 20, “Power Interface” on page 46
252479-007US
IXP42X product line and IXC1100 control plane processors
Symbol
PWR
GND
N/C
VO
PD
ID
VI
PE
Tri
H
1
0
X
Z
L
-
Power pin
Ground pin
Driven to Vcc
Driven to Vss
Driven to unknown state
Input is disabled
Pulled up to Vcc
Pulled to Vss
Pull-up Disabled
Output Disabled
A valid output level is driven, allowed states - 1, 0, H, Z
Need to drive a valid input level, allowed states - 1, 0, H, Z
Pull-up Enabled, equivalent to H
Output Only/Tristatable
No Connect
Pin must be connected as described
Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Reference
Description
Datasheet
31

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