PRIXP425BC 869083 Intel, PRIXP425BC 869083 Datasheet - Page 106

PRIXP425BC 869083

Manufacturer Part Number
PRIXP425BC 869083
Description
Manufacturer
Intel
Datasheet

Specifications of PRIXP425BC 869083

Core Operating Frequency
400MHz
Package Type
BGA
Pin Count
492
Mounting
Surface Mount
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Lead Free Status / Rohs Status
Compliant
Table 58.
Figure 32.
Intel
Datasheet
106
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Motorola* Simplex
Read Mode
EX_CLK
EX_CS_N[0]
EX_ADDR[23:0]
EX_ALE
EX_IOWAIT_N
EX_RD_N
(exp_mot_rnw)
EX_WR_N
(exp_mot_ds_n)
EX_DATA[15:0]
Motorola* Multiplexed Mode Values (Sheet 2 of 2)
Motorola* Simplex Read Mode
Symbol
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
T
dholdafterds
T
T
ale2valcs
T
T
rdsetup
rdhold
recov
The EX_ALE signal is extended from 1 to 4 cycles based on the programming of the T1 timing
parameter. The parameter Tale2addrhold is fixed at 1 cycle.
Setting the address phase parameter (T1) will adjust the duration that the address appears to the
external device.
Setting the data setup phase parameter (T2) will adjust the duration that the data appears prior to a
data strobe (read or write) to an external device.
Setting the data strobe phase parameter (T3) will adjust the duration that the data strobe appears
(read or write) to an external device. Data will be available during this time as well.
Setting the data hold strobe phase parameter (T4) will adjust the duration that the chip selects,
address, and data (during a write) will be held.
Setting the recovery phase parameter (T5) will adjust the duration between successive accesses on the
expansion interface.
One cycle is the period of the Expansion Bus clock.
Clock to output delay for all signals will be a maximum of 15 ns for devices requiring operation in
synchronous mode.
Timing tests were performed with a 70-pF capacitor to ground.
Parameter
Valid data after the rising edge of EXP_MOT_DS_N
Valid chip select after the falling edge of EX_ALE
Data valid required before the rising edge of EXP_MOT_DS_N
Data hold required after the rising edge of EXP_MOT_DS_N
Time needed between successive accesses on expansion
interface.
1-4 Cycles
T
T1
ad2valcs
Intel
1-4 Cycles
T2
®
IXP42X product line and IXC1100 control plane processors
Valid Address
1-16 Cycles
Valid Data
T
T3
rdsetup
1-4 Cycles
T
rdhold
T4
Document Number: 252479-006US
1-16 Cycles
Min.
T
15
1
1
0
1
T5
recov
Max.
16
4
4
B3753-001
Units
Cycles
Cycles
Cycles
ns
ns
August 2006
Notes
5,
7
6
7

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