PRIXP425BC 869083 Intel, PRIXP425BC 869083 Datasheet - Page 112

PRIXP425BC 869083

Manufacturer Part Number
PRIXP425BC 869083
Description
Manufacturer
Intel
Datasheet

Specifications of PRIXP425BC 869083

Core Operating Frequency
400MHz
Package Type
BGA
Pin Count
492
Mounting
Surface Mount
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Lead Free Status / Rohs Status
Compliant
Table 62.
Intel
Datasheet
112
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
HPI-16 Multiplexed Write Accesses Values
Notes:
1.
2.
3.
4.
5.
6.
7.
T
T
T
T
T
Symbol
cs2hds1val
hds1_pulse
data_setup
add_setup
data_hold
T
recov
The address phase parameter (T1) must be set to a minimum value of 2. This value allows three T
clocks for the address phase. This setting is required to ensure that in the event of an HRDY, the
Intel
recognize the HRDY and hold the address phase for at least one clock pulse after the HRDY is de-
active.
The data setup phase parameter (T2) must be set to a minimum value of 2. This value allows three T
clocks for setup phase.
The data strobe phase parameter (T3) must be set to a minimum value of 1. This value allows two T
clocks for the data phase. This setting is required to ensure that in the event of an HRDY, the Intel
IXP42X Product Line and Intel
recognize the HRDY and hold the data setup phase for at least one clock pulse after the HRDY is de-
active.
Setting the recovery phase parameter (T5) will adjust the duration between successive accesses on
the Expansion Bus interface.
HRDY can be asserted by the DSP at any point in the access. The interface will not leave states T1 or
T3 until HRDY is de-active.
One cycle is the period of the Expansion Bus clock.
Timing tests were performed with a 70-pF capacitor to ground.
®
IXP42X Product Line and Intel
Valid time that address is asserted on the line. The address
is asserted at the same time as chip select.
Delay from chip select being active and the HDS1 data
strobe being active.
Pulse width of the HDS1 data strobe.
Data valid prior to the rising edge of the HDS1 data strobe.
Data valid after the rising edge of the HDS1 data strobe.
Time required between successive accesses on the
expansion interface.
Intel
®
Parameter
IXC1100 Control Plane processors has had sufficient time to
®
IXP42X product line and IXC1100 control plane processors
®
IXC1100 Control Plane processors has had sufficient time to
Document Number: 252479-006US
Min.
11
3
4
2
4
4
Max.
45
36
17
4
5
5
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Units
August 2006
1, 5,
2, 4,
3, 5,
Notes
5,
3,
4,
6
6
6
®
6
5
6

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