PRIXP425BC 869083 Intel, PRIXP425BC 869083 Datasheet - Page 25
Manufacturer Part Number
Specifications of PRIXP425BC 869083
Core Operating Frequency
Operating Temperature (max)
Operating Temperature (min)
Operating Temperature Classification
Lead Free Status / Rohs Status
Document Number: 252479-006US
IXP42X product line and IXC1100 control plane processors
The expansion bus interface is an asynchronous interface to externally connected
chips. However, a clock must be supplied to the IXP42X product line and IXC1100
control plane processors’ expansion bus interface for the interface to operate. This
clock can be driven from GPIO 15 or an external source. The maximum clock rate that
the expansion bus interface can accept is 66.66 MHz.
At the de-assertion of reset, the 24-bit address bus is used to capture configuration
information from the levels that are applied to the pins at this time. External pull-up/
pull-down resistors are used to tie the signals to particular logic levels. For additional
details, refer to Section 8 (Expansion Bus Controller) of the Intel
of Network Processors and IXC1100 Control Plane Processor Developer’s Manual.)
High-Speed, Serial Interfaces
The high-speed, serial interfaces are six-signal interfaces that support serial transfer
speeds from 512 KHz to 8.192 MHz, for some models of the IXP42X product line and
IXC1100 control plane processors. (See
Each interface allows direct connection of up to four T1/E1 framers and CODEC/SLICs
to the IXP42X product line and IXC1100 control plane processors. The high-speed,
serial interfaces are capable of supporting various protocols, based on the
implementation of the code developed for the network processor engine. For a list of
supported protocols, see the Intel
High-Speed and Console UARTs
The UART interfaces are 16550-compliant UARTs with the exception of transmit and
receive buffers. Transmit and receive buffers are 64 bytes-deep versus the 16 bytes
required by the 16550 UART specification.
The interface can be configured to support speeds from 1,200 baud to 921 Kbaud. The
interface support configurations of:
The request-to-send (RTS_N) and clear-to-send (CTS_N) modem control signals also
are available with the interface for hardware flow control.
16 GPIO pins are supported by the IXP42X product line and IXC1100 control plane
processors. GPIO pins 0 through 15 can be configured to be general-purpose input or
general-purpose output. Additionally, GPIO pins 0 through 12 can be configured to be
an interrupt input.
GPIO Pin 14 and GPIO 15 can also be configured as a clock output. The output-clock
configuration can be set at various speeds, up to 33.33 MHz, with various duty cycles.
GPIO Pin 14 is configured as an input, upon reset. GPIO Pin 15 is configured as an
output, upon reset. GPIO Pin 15 can be used to clock the expansion interface, after
Internal Bus Performance Monitoring Unit (IBPMU)
The IXP42X product line and IXC1100 control plane processors consists of seven 27-bit
counters that may be used to capture predefined durations or occurrence events on the
North AHB, South AHB, or SDRAM controller page hits/misses.
• Five, six, seven, or eight data-bit transfers
• One or two stop bits
• Even, odd, or no parity
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
IXP400 Software Programmer’s Guide.
Table 4 on page
IXP42X Product Line