PRIXP425BC 869083 Intel, PRIXP425BC 869083 Datasheet - Page 29

• Manufacturer Part Number: PRIXP425BC 869083
• Manufacturer: Intel

Specifications of PRIXP425BC 869083

• Core Operating Frequency: 400MHz
• Package Type: BGA
• Pin Count: 492
• Mounting: Surface Mount
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

Intel
2.2.3
2.2.4
2.2.5
August 2006
Document Number: 252479-006US
®
IXP42X product line and IXC1100 control plane processors
Successfully predicted branches avoid any branch-latency penalties in the super
pipeline. Unsuccessfully predicted branches result in a four to five cycle branch-latency
penalty in the super pipeline.
Instruction Memory Management Unit (IMMU)
For instruction pre-fetches, the IMMU controls logical-to-physical address translation,
memory access permissions, memory-domain identifications, and attributes (governing
operation of the instruction cache). The IMMU contains a 32-entry, fully associative
instruction-translation, look-aside buffer (ITLB) that has a round-robin replacement
policy. ITLB entries zero through 30 can be locked.
When an instruction pre-fetch misses in the ITLB, the IMMU invokes an automatic
table-walk mechanism that fetches an associated descriptor from memory and loads it
into the ITLB. The descriptor contains information for logical-to-physical address
translation, memory-access permissions, memory-domain identifications, and
attributes governing operation of the I-cache. The IMMU then continues the instruction
pre-fetch by using the address translation just entered into the ITLB. When an
instruction pre-fetch hits in the ITLB, the IMMU continues the pre-fetch using the
address translation already resident in the ITLB.
Access permissions for each of up to 16 memory domains can be programmed. When
an instruction pre-fetch is attempted to an area of memory in violation of access
permissions, the attempt is aborted and a pre-fetch abort is sent to the Intel XScale
processor for exception processing. The IMMU and DMMU can be enabled or disabled
together.
Data Memory Management Unit (DMMU)
For data fetches, the DMMU controls logical-to-physical address translation, memory-
access permissions, memory-domain identifications, and attributes (governing
operation of the data cache or mini-data cache and write buffer). The DMMU contains a
32-entry, fully associative data-translation, look-aside buffer (DTLB) that has a round-
robin replacement policy. DTLB entries 0 through 30 can be locked.
When a data fetch misses in the DTLB, the DMMU invokes an automatic table-walk
mechanism that fetches an associated descriptor from memory and loads it into the
DTLB. The descriptor contains information for logical-to-physical address translation,
memory-access permissions, memory-domain identifications, and attributes (governing
operation of the D-cache or mini-data cache and write buffer).
The DMMU continues the data fetch by using the address translation just entered into
the DTLB. When a data fetch hits in the DTLB, the DMMU continues the fetch using the
address translation already resident in the DTLB.
Access permissions for each of up to 16 memory domains can be programmed. When a
data fetch is attempted to an area of memory in violation of access permissions, the
attempt is aborted and a data abort is sent to the Intel XScale
processing.
The IMMU and DMMU can be enabled or disabled together.
Instruction Cache (I-Cache)
The I-cache can contain high-use, multiple-code segments or entire programs, allowing
the Intel XScale
processor stalls caused by multi-cycle accesses to external memory.
®
processor access to instructions at core frequencies. This prevents
Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
®
processor for exception
Datasheet
®
29