PRIXP425BC 869083 Intel, PRIXP425BC 869083 Datasheet - Page 40

• Manufacturer Part Number: PRIXP425BC 869083
• Manufacturer: Intel

Specifications of PRIXP425BC 869083

• Core Operating Frequency: 400MHz
• Package Type: BGA
• Pin Count: 492
• Mounting: Surface Mount
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

Table 11.
Intel
Datasheet
40
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
MII Interfaces (Sheet 1 of 2)
ETH_TXCLK0
ETH_TXDATA0[3:0]
ETH_TXEN0
ETH_RXCLK0
ETH_RXDATA0[3:0]
ETH_RXDV0
ETH_COL0
ETH_CRS0
ETH_MDIO
ETH_MDC
†
††
Name
For a legend of the Type codes, see
For new designs, this signal should be pulled high with a 10-KΩ resistor when not being utilized in the
system. No change is required to existing designs that have this signal pulled low.
Power
or Sys
Reset
Reset
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Reset
Post
VI
VI
VI
VI
VI
VI
Z
Z
0
0
Intel
Type
®
I/O
IO
O
O
I
I
I
I
I
I
IXP42X product line and IXC1100 control plane processors
Table 5 on page
†
Externally supplied transmit clock.
Should be pulled high
being utilized in the system.
Transmit data bus to PHY, asserted synchronously with
respect to ETH_TXCLK0.
Indicates that the PHY is being presented with nibbles on
the MII interface. Asserted synchronously, with respect to
ETH_TXCLK0, at the first nibble of the preamble and
remains asserted until all the nibbles of a frame are
presented.
Externally supplied receive clock.
Should be pulled high
being utilized in the system.
Receive data bus from PHY, data sampled synchronously
with respect to ETH_RXCLK0
Receive data valid, used to inform the MII interface that the
Ethernet PHY is sending data. Should be pulled high
through a 10-KΩ resistor when not being utilized in the
system.
Asserted by the PHY when a collision is detected by the
PHY. Should be pulled low through a 10-KΩ resistor when
not being utilized in the system.
Asserted by the PHY when the transmit medium or receive
medium is active. De-asserted when both the transmit and
receive medium are idle. Remains asserted throughout the
duration of a collision condition. PHY asserts CRS
asynchronously and de-asserts synchronously, with respect
to ETH_RXCLK0. Should be pulled high
resistor when not being utilized in the system.
Management data output. Provides the write data to both
PHY devices connected to each MII interface.
An external 1.5-KΩ pull-up resistor is required.
Note:
Should be pulled high
being utilized in the system.
Management data clock. Management data interface clock
is used to clock the MDIO signal as an output and sample
the MDIO as an input. The ETH_MDC is an input on power
up and can be configured to be an output through an Intel
API as documented in the Intel
Programmer’s Guide.
• 25 MHz for 100 Mbps operation
• 2.5 MHz for 10 Mbps
• 25 MHz for 100 Mbps operation
• 2.5 MHz for 10 Mbps
• Should be pulled high
not being utilized in the system.
If interfacing with a single Intel
Ethernet Transceiver, and a 1.5K pull-up resistor is
not used, the NPE will ‘see’ 32 PHYs on the MII
interface.
33.
††
††
††
Description
through a 10-KΩ resistor when not
through a 10-KΩ resistor when not
through a 10-KΩ resistor when not
Document Number: 252479-006US
††
through a 10-KΩ resistor when
®
IXP400 Software
††
®
through a 10-KΩ
LXT972 Fast
August 2006
††